ST72324BXX Datasheet, PDF (118/188 Pages) STMicroelectronics – 8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI

On-chip peripherals
ST72324B
Table 62. SCICR1 register description (continued)
Bit Name
Function
Parity Selection
1 PS
This bit selects the odd or even parity when the parity generation/detection is
enabled (PCE bit set). It is set and cleared by software. The parity will be selected
after the current byte.
0: Even parity
1: Odd parity
Parity Interrupt Enable
0 PIE
This bit enables the interrupt capability of the hardware parity control when a parity
error is detected (PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
1: Parity error interrupt enabled
SCI Control Register 2 (SCICR2)
SCICR2
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 63. SCICR2 register description
Bit Name
Function
Transmitter Interrupt Enable
7 TIE
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR register.
Transmission Complete Interrupt Enable
6 TCIE
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC = 1 in the SCISR register.
Receiver interrupt Enable
5 RIE
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR = 1 or RDRF = 1 in the SCISR
register.
Idle Line Interrupt Enable
4 ILIE
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE = 1 in the SCISR register.
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