ST72325_07 Datasheet, PDF (116/196 Pages) STMicroelectronics – 8-bit MCU with 16 to 60K Flash/ROM, ADC, CSS, 5 timers, SPI, SCI, I2C interface

SERIAL COMMUNICATIONS INTERFACE (Cont’d)
DATA REGISTER (SCIDR)
Read/Write
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
7
0
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock in convention-
al Baud Rate Generator mode.
TR dividing factor
1
2
SCT2
0
0
SCT1
0
0
SCT0
0
1
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
4
0
1
0
8
0
1
1
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 63).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 63).
16
1
0
0
32
1
0
1
64
1
1
0
128
1
1
1
Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP[1:0] bits
define the total division applied to the bus clock to
yield the receive rate clock in conventional Baud
Rate Generator mode.
BAUD RATE REGISTER (SCIBRR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
Bits 7:6 = SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
RR Dividing factor
1
2
4
8
16
32
64
128
SCR2
0
0
0
0
1
1
1
1
SCR1
0
0
1
1
0
0
1
1
SCR0
0
1
0
1
0
1
0
1
PR Prescaling factor
1
3
4
13
SCP1
0
0
1
1
SCP0
0
1
0
1
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