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| ST7LITE2 Datasheet, PDF (113/131 Pages) STMicroelectronics – 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI | |||
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ST7LITE2
13.9 CONTROL PIN CHARACTERISTICS
13.9.1 Asynchronous RESET Pin
TA = -40°C to 125°C, unless otherwise specified
Symbol
Parameter
Conditions
Min Typ Max Unit
VIL
VIH
Vhys
Input low level voltage
Input high level voltage
Schmitt trigger voltage hysteresis 1)
VOL Output low level voltage 2)
RON Pull-up equivalent resistor 3) 1)
tw(RSTL)out Generated reset pulse duration
th(RSTL)in External reset pulse hold time 4)
tg(RSTL)in Filtered glitch duration 5)
0.7xVDD
VDD=5V
IIO=+5mA TAâ¤85°C
TAâ¥85°C
IIO=+2mA TAâ¤85°C
TAâ¥85°C
VDD=5V
20
VDD=3V.
40
Internal reset sources
20
0.3xVDD V
2
V
0.5
1.0
1.2
V
0.2
0.4
0.5
40
80
kâ¦
70 120
30
µs
µs
200
ns
Figure 88. Typical Application with RESET pin 6)7)8)
Recommended
if LVD is disabled
VDD
VDD
VDD
RON
ST72XXX
USER
EXTERNAL
RESET
CIRCUIT 5)
0.01µF
4.7kâ¦
0.01µF
Required if LVD is disabled
Filter
PULSE
GENERATOR
INTERNAL
RESET
WATCHDOG
LVD RESET
Notes:
1. Data based on characterization results, not tested in production.
2. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between
VILmax and VDD
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below th(RSTL)in can be ignored.
5. The reset network (the resistor and two capacitors) protects the device against parasitic resets especially in noisy en-
vironments.
6. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
7. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the VIL max. level specified in section 13.9.1 on page 113. Otherwise the reset will not be taken into account internally.
8. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin (by an external pull-p for example) is less than the absolute maximum value spec-
ified for IINJ(RESET) in section 13.2.2 on page 92.
113/131
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