ST72334J_03 Datasheet, PDF (112/153 Pages) STMicroelectronics – 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES

ST72334J/N, ST72314J/N, ST72124J
FUNCTIONAL OPERATING CONDITIONS (Cont’d)
Figure 60. High LVD Threshold Versus V_DD and f_OSC for ROM devices ²⁾
DEVICE UNDER
RESET
IN THIS AREA
f_{OSC1680[MH00000 00000}z₀₀₀₀₀] _{00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000}
2.5
3
3.5 ^{VIT-≥3.85} 4
4.5
5
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
FUNCTIONAL AREA
SUPPLY VOLTAGE [V]
5.5
Figure 61. Medium LVD Threshold Versus V_DD and f_OSC for ROM devices ²⁾
DEVICE UNDER
RESET
IN THIS AREA
f_{OSC168[MH00000 00000}z₀₀₀₀₀] _{00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000}
0
2.5
3
V_IT-≥3.5V
4
4.5
5
Figure 62. Low LVD Threshold Versus V_DD and f_OSC for ROM devices ²⁾³⁾
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
FUNCTIONAL AREA
SUPPLY VOLTAGE [V]
5.5
f_OSC [MHz]
FUNCTIONALITY
NOT GUARANTEED
DEVICE UNDER
RESET
IN THIS AREA
16
8
000
000
000
000
000
000
000
000
000
000
000
000
0
IN THIS AREA
FUNCTIONAL AREA
SUPPLY VOLTAGE [V]
2.5
V_IT-≥3.00V 3.5
4
4.5
5
5.5
Notes:
1. LVD typical data are based on T_A=25°C. They are given only as design guidelines and are not tested.
2. The minimum V_DD rise time rate is needed to insure a correct device power-on and LVD reset. Not tested in production.
3. If the low LVD threshold is selected, when V_DD falls below 3.2V, (V_DD minimum operating voltage), the device is guar-
anteed to continue functioning until it goes into reset state. The specified V_DD min. value is necessary in the device power
on phase, but during a power down phase or voltage drop the device will function below this min. level.
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