AN2606 Datasheet, PDF (112/155 Pages) STMicroelectronics – STM32 microcontroller system memory boot mode

STM32F411xx devices bootloader
26 STM32F411xx devices bootloader
AN2606
26.1
Bootloader configuration
The STM32F411xx bootloader is activated by applying pattern1 (described in Table 2:
Bootloader activation patterns). The following table shows the hardware resources used by
this bootloader.
Table 56. STM32F411xx configuration in System memory boot mode
Bootloader
Feature/Peripheral
State
Comment
RCC
HSI enabled
HSE enabled
The system clock frequency is 60 MHz
using the PLL.
The HSI clock source is used at startup
(interface detection phase) and when
USART or SPI or I2C interfaces are
selected (once DFU bootloader is selected,
the clock source will be derived from the
external crystal).
The system clock frequency is 60 MHz.
The HSE clock source is used only when
the DFU (USB FS Device) interfaces are
selected.
The external clock must provide a fre-
quency multiple of 1 MHz and ranging from
4 MHz to 26 MHz.
-
Common to all
bootloaders
RAM
-
The Clock Security System (CSS) interrupt
is enabled for the CAN and DFU bootload-
ers. Any failure (or removal) of the external
clock generates system reset.
12 Kbytes starting from address
0x20000000 are used by the bootloader
firmware
System memory
-
IWDG
-
30424 bytes starting from address
0x1FFF0000, contain the bootloader firm-
ware
The independent watchdog (IWDG) pres-
caler is configured to its maximum value. It
is periodically refreshed to prevent watch-
dog reset (in case the hardware IWDG
option was previously enabled by the user).
Power
-
Voltage range is set to [1.62 V, 2.1 V]. In
this range internal Flash write operations
are allowed only in byte format (Half-Word,
Word and Double-Word operations are not
allowed). The voltage range can be config-
ured in run time using bootloader com-
mands.
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