ST7265X Datasheet, PDF (110/166 Pages) STMicroelectronics – LOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, I2C, SPI

ST7265x
I²C SINGLE MASTER BUS INTERFACE (Cont’d)
Acknowledge may be enabled and disabled by
software.
The speed of the I²C interface may be selected
between Standard (0-100KHz) and Fast I²C (100-
400KHz).
SDA/SCL Line Control
Transmitter mode: the interface holds the clock
line low before transmission to wait for the micro-
controller to write the byte in the Data Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
Figure 67. I²C Interface Block Diagram
The SCL frequency (F_scl) is controlled by a pro-
grammable clock divider which depends on the
I²C bus mode.
When the I2C cell is enabled, the SDA and SCL
ports must be configured as floating open-drain
output or floating input. In this case, the value of
the external pull-up resistance used depends on
the application.
When the I2C cell is disabled, the SDA and SCL
ports revert to being standard I/O port pins.
SDA
SDAI
DATA CONTROL
DATA REGISTER (DR)
DATA SHIFT REGISTER
SCLI
SCL
CLOCK CONTROL
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR)
STATUS REGISTER 1 (SR1)
STATUS REGISTER 2 (SR2)
CONTROL LOGIC
INTERRUPT
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