VNQ5027AK-E Datasheet, PDF (11/31 Pages) STMicroelectronics – Quad channel high side driver with analog current sense for automotive applications

VNQ5027AK-E
Electrical specifications
Table 8. Current Sense (8V<V_CC<16V) (continued)
Symbol
Parameter
Test conditions
V_SENSEH
I_SENSEH
t_DSENSE1H
t_DSENSE1L
t_DSENSE2H
Δt_DSENSE2H
t_DSENSE2L
Analog sense output voltage in
over temperature condition
V_CC= 13V; R_SENSE= 3.9KΩ
Analog sense output current in
over temperature condition
V_CC= 13V; V_SENSE= 5V
Delay response time from
falling edge of CS_DIS pin
V_SENSE<4V, 0.5A<Iout<10A
I_SENSE= 90% of I_{SENSE max}
(see Figure 4.)
Delay response time from
rising edge of CS_DIS pin
V_SENSE<4V, 0.5A<Iout<10A
I_SENSE=10% of I_{SENSE max}
(see Figure 4.)
Delay response time from
rising edge of INPUT pin
V_SENSE<4V, 0.5A<Iout<10A
I_SENSE=90% of I_{SENSE max}
(see Figure 4.)
Delay response time between
rising edge of output current
and rising edge of current
sense
Delay response time from
falling edge of input pin
V_SENSE < 4V,
I_SENSE = 90% of I_SENSEMAX,
I_OUT = 90% of I_OUTMAX
I_OUTMAX=2A (see Figure 5)
V_SENSE<4V, 0.5A<Iout<10A
I_SENSE=10% of I_{SENSE max}
(see Figure 4.)
1. Parameter guaranteed by design; it is not tested.
Min. Typ. Max. Unit
9
V
8
mA
50 100 µs
5
20 µs
70 300 µs
200 µs
100 250 µs
Table 9.
Symbol
Protection⁽¹⁾
Parameter
Test conditions
Min. Typ. Max. Unit
I_limH
DC short circuit current ^VCC=13V
5V<V_CC<36V
I_limL
Short circuit current
during thermal cycling
V_CC=13V; T_R<T_j<T_TSD
T_TSD
T_R
T_RS
Shutdown temperature
Reset temperature
Thermal reset of
STATUS
T_HYST
Thermal hysteresis
(T_TSD-T_R)
V_DEMAG
Turn-off output voltage
clamp
I_OUT= 2A; V_IN=0; L=6mH
V_ON
Output voltage drop
limitation
I_OUT=0.2A; T_j=-40°C...150°C
(see Figure 9.)
29
42
59
A
59
A
16
A
150 175 200 °C
T_RS + 1 T_RS + 5
°C
135
°C
7
°C
V_CC-41 V_CC-46 V_CC-52 V
25
mV
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
Doc ID 12730 Rev 6
11/31