TDA7310 Datasheet, PDF (11/15 Pages) STMicroelectronics – SERIAL BUS CONTROLLED AUDIO PROCESSOR

TDA7310
APPLICATION INFORMATION (continued)
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the µP can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.
This approach of course is less protected from
misworking and decreases the noise immunity.
Interface Protocol
The interface protocol comprises:
A start condition (s)
A chip address byte, containing the TDA7310
address (the 8th bit of the byte must be 0). The
TDA7310 must always acknowledge at the end
of each transmitted byte.
A sequence of data (N-bytes + acknowledge)
A stop condition (P)
TDA7310 ADDRESS
MSB first byte
LSB MSB
S 1 0 0 0 1 0 A 0 ACK
ACK = Acknowledge
S = Start
P = Stop
MAX CLOCK SPEED 100kbits/s
DATA
LSB MSB
ACK
DATA
Data Transferred (N-bytes + Acknowledge)
LSB
ACK P
SOFTWARE SPECIFICATION
Chip address
1
0
0
0
1
0
MSB
A = LOGIC LEVEL ON PIN ADDR
A
0
LSB
DATA BYTES
MSB
0
0
1
1
1
1
1
0
1
0
0
1
0
1
0
1
B2
B1
B0
A2
A1
0
B1
B0
A2
A1
1
B1
B0
A2
A1
0
B1
B0
A2
A1
1
B1
B0
A2
A1
0
G1
G0
S2
S1
1
0
C3
C2
C1
1
1
C3
C2
C1
Ax = 1.25dB steps; Bx = 10dB steps; Cx = 2dB steps; Gx = 6.25dB steps
STATUS AFTER POWER ON RESET
Volume
speaker
audio Switch
bass
treble
gain
-77.5dB
-37.5dB
Stereo 5
+2dB
+2dB
0dB
LSB
FUNCTION
A0
Volume control
A0
Speaker ATT LR
A0
Speaker ATT RR
A0
Speaker ATT LF
A0
Speaker ATT RF
S0
Audio switch
C0
Bass control
C0
Treble control
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