STP16CPPS05 Datasheet, PDF (11/31 Pages) STMicroelectronics – 16 constant current output channels

STP16CPPS05
Timing diagrams
5
Timing diagrams
Table 9: Truth table
CLOCK LE OE SERIAL-IN OUT0 ............. OUT7 ................ OUT15
SDO
_|¯
H
L
_|¯
L
L
_|¯
H
L
¯|_
X
L
¯|_
X
H
Dn
Dn + 1
Dn + 2
Dn + 3
Dn + 3
Dn ..... Dn - 7 ..... Dn -15
No change
Dn + 2 ..... Dn - 5 ..... Dn -13
Dn + 2 ..... Dn - 5 ..... Dn -13
OFF
Dn - 15
Dn - 14
Dn - 13
Dn - 13
Dn - 13
OUTn = ON when Dn = H OUTn = OFF when Dn = L.
Figure 7: Timing diagram
1 Latch and output enable terminals are level-sensitive and are not synchronized
with rising or falling edge of CLK signal.
2 When LE terminal is low level, the latch circuit holds previous set of data.
3 When LE terminal is high level, the latch circuit refreshes new set of data from
SDI chain.
4 When OE terminal is at low level, the output terminals Out 0 to Out 15
respond to data in the latch circuits, either ‘1’ for ON or ‘0’ for OFF.
5 When OE terminal is at high level, all output terminals are switched OFF.
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