STM32F107VCT6 Datasheet, PDF (11/103 Pages) STMicroelectronics – 64 to 256 Kbytes of Flash memory

STM32F105xx, STM32F107xx
Description
2.2
Full compatibility throughout the family
The STM32F105xx and STM32F107xx constitute the connectivity line family whose
members are fully pin-to-pin, software and feature compatible.
The STM32F105xx and STM32F107xx are a drop-in replacement for the low-density
(STM32F103x4/6), medium-density (STM32F103x8/B) and high-density
(STM32F103xC/D/E) performance line devices, allowing the user to try different memory
densities and peripherals providing a greater degree of freedom during the development
cycle.
Table 3. STM32F105xx and STM32F107xx family versus STM32F103xx family⁽¹⁾
STM32
Low-density
Medium-density
device STM32F103xx devices STM32F103xx devices
High-density
STM32F103xx devices
STM32F105xx
STM32F107xx
Flash
size (KB)
16
32
32
64 128 256 384 512 64 128 256 128 256
RAM
size (KB)
6
10
10
20 20
48
64
64 64 64 64 64
64
144 pins
100 pins
2 × USARTs
64 pins _{2 × 16-bit timers}
1 × SPI, 1 × I²C, USB,
CAN,
1 × PWM timer
2 × ADCs
48 pins
5 × USARTs,
5 × USARTs
4 × 16-bit timers,
3 × USARTs
2 × USARTs 3 × 16-bit
2 × 16-bit ^timers
timers
1 × SPI,
1 × I²C,
2 × SPIs,
2 × I²Cs, USB,
CAN,
USB, CAN, ^{1 × PWM timer}
4 × 16-bit timers,
2 × basic timers,
2
2
×
×
basic
I²Ss,
timers, 3
2 × I2Cs,
× SPIs,
USB,
3
2
×
×
SPIs,
I²Ss,
CAN, 2 × PWM timers _{2 × I2Cs,}
3 × ADCs, 2 × DACs,
USB OTG FS,
1 × SDIO, FSMC (100-
and 144-pin packages⁽²⁾)
2 × CANs,
1 × PWM timer,
1 × PWM 2 × ADCs
2 × ADCs,
timer
2 × DACs
2 × ADCs
36 pins
5 × USARTs,
4 × 16-bit timers,
2 × basic timers,
3 × SPIs,
2 × I²S,
1 × I2C,
USB OTG FS,
2 × CANs,
1 × PWM timer,
2 × ADCs,
2 × DACs,
Ethernet
1. Please refer to Table 5: Pin definitions for peripheral availability when the I/O pins are shared by the peripherals required
by the application.
2. Ports F and G are not available in devices delivered in 100-pin packages.
Doc ID 15274 Rev 6
11/104