PM6670 Datasheet, PDF (11/53 Pages) STMicroelectronics – Complete DDR2/3 memory power supply controller

PM6670
Table 6. Electrical characteristics (continued)
Symbol
Parameter
Test condition
Soft end section
VDDQ Discharge resistance
in non-tracking discharge
mode
VTT discharge resistance in
non-tracking discharge mode
VTTREF discharge
resistance in non-tracking
discharge mode
VDDQ Output threshold
synchronous for final tracking
to non-tracking discharge
transition
V_TT LDO section
I_LDOIN,ON
LDO input bias current in
full-on state
S3 = S5 = +5V, No Load on VTT
I_LDOIN, LDO input bias current in
STR ^{suspend-to-RAM state}
I_LDOIN, LDO input bias current in
STD ^{suspend-to-disk state}
I_{VTTSNS, VTTSNS bias current}
BIAS
S3 = 0V, S5 = +5V,
No Load on VTT
S3 = S5 = 0V, No Load on VTT
S3 = +5V, S5 = +5V,
V_VTTSNS = V_VSNS /2
I_{VTTSNS, VTTSNS leakage current}
LEAK
S3 = 0V, S5 = +5V,
V_VTTSNS = V_VSNS /2
I_VTT,LEAK VTT leakage current
S3 = 0V, S5 = +5V,
V_VTT = V_VSNS /2
LDO linear regulator output S3 = S5= +5V, I_VTT = 0A,
voltage (DDR2)
MODE = DDRSEL = +5V
LDO linear regulator output S3 = S5= +5V, I_VTT = 0A,
voltage (DDR3)
MODE = +5V, DDRSEL = 0V
V_VTT
S3 = S5 = MODE = + 5V,
-1mA < I_VTT < 1mA
LDO output accuracy respect S3 = S5 = MODE = +5V,
to VTTREF
-1A < I_VTT < 1A
S3 = S5 = MODE = +5V,
-2A < I_VTT < 2A
LDO source current limit
I_VTT,CL
LDO sink current limit
V_VTT < 1.10*( V_VSNS /2)
V_VTT > 1.10*( V_VSNS /2)
V_VTT > 0.90*( V_VSNS /2)
V_VTT < 0.90*( V_VSNS /2)
Electrical characteristics
Values
Unit
Min Typ Max
15
25
35
Ω
15
25
35
1
1.5
2
kΩ
0.2
0.4
0.6
V
1
10
10
1
µA
1
1
-10
10
0.9
V
0.75
-20
20
-25
25
mV
-35
35
2
2.3
2.8
1
1.15 1.4
-2.8 -2.3
-2
-1.4 -1.15 -1
A
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