M48Z02_07 Datasheet, PDF (11/20 Pages) STMicroelectronics – 5V, 16Kbit (2Kb x 8) ZEROPOWER SRAM

M48Z02, M48Z12
Figure 7. Checking the BOK flag status
POWER-UP
READ DATA
AT ANY ADDRESS
WRITE DATA
COMPLEMENT BACK
TO SAME ADDRESS
READ DATA
AT SAME
ADDRESS AGAIN
Operation modes
IS DATA
COMPLEMENT
OF FIRST
READ?
(BATTERY OK) YES
WRITE ORIGINAL
DATA BACK TO
SAME ADDRESS
NO (BATTERY LOW)
NOTIFY SYSTEM
OF LOW BATTERY
(DATA MAY BE
CORRUPTED)
CONTINUE
AI00607
2.4
V_CC noise and negative going transients
I_CC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the V_CC bus. These transients can be reduced if
capacitors are used to store energy which stabilizes the V_CC bus. The energy stored in the
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in
Figure 8 on page 12) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on V_CC that drive it to values below V_SS by as much as
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, STMicroelectronics recommends
connecting a schottky diode from V_CC to V_SS (cathode connected to V_CC, anode to V_SS).
Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is
recommended for surface mount.
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