M36W0R6050T1 Datasheet, PDF (11/22 Pages) STMicroelectronics – 64 Mbit (4 Mb ×16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb ×16) PSRAM, multi-chip package

M36W0R6050T1, M36W0R6050B1
Signal descriptions
2.12
PSRAM Chip Enable (E2_P)
When de-asserted (Low), the Chip Enable input E2_P, puts the device in Power-Down mode.
This is the lowest power mode according to the Configuration Register settings (see
M69KB048BD datasheet).
2.13
PSRAM Output Enable (G_P)
The Output Enable, G_P, provides a high speed tri-state control, allowing fast read/write
cycles to be achieved with the common I/O data bus.
2.14
PSRAM Write Enable (W_P)
The Write Enable, W_P, controls the Bus Write operation of the memory’s Command
Interface.
2.15
PSRAM Upper Byte Enable (UB_P)
The Upper Byte Enable, UB_P, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-
DQ15) to or from the upper part of the selected address during a Write or Read operation.
2.16
PSRAM Lower Byte Enable (LB_P)
The Lower Byte Enable, LB_P, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-
DQ7) to or from the lower part of the selected address during a Write or Read operation.
2.17
V_DDF supply voltage
V_DDF provides the power supply to the internal core of the Flash memory component. It is
the main power supplies for all Flash memory operations (Read, Program and Erase).
2.18
V_DDP supply voltage
The V_DDP Supply Voltage supplies the power for all operations (Read or Write) and for
driving the refresh logic, even when the device is not being accessed.
2.19
V_DDQF supply voltage
V_DDQF provides the power supply for the Flash memory I/O pins. This allows all Outputs to
be powered independently of the Flash memory core power supply, V_DDF.
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