M24C16-A125 Datasheet, PDF (11/37 Pages) STMicroelectronics – Automotive 16-Kbit serial IC bus EEPROM with 1 MHz clock

M24C16-A125
Device operation
3.5
Device addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, as
shown in Table 2 (on Serial Data (SDA), most significant bit first).
Table 2. Device select code
Device type identifier ⁽¹⁾
Chip Enable address
RW
b7
b6
b5
b4
b3
b2
b1
b0
When accessing the
memory
1
0
1
0
A10
A9
A8
RW
When accessing the
identification page
1
0
1
1
X
X
X
RW
1. The most significant bit, b7, is sent first.
The 8^th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding memory device gives an
acknowledgment on Serial Data (SDA) during the 9^th bit time. If the memory device does not
match the device select code, it deselects itself from the bus, and goes into Standby mode.
Table 3. Significant address bits
Memory
(Device type identifier = 1010b)
Identification page
(Device type identifier = 1011b)
Random
Address Read
b3 ⁽¹⁾
A10
b2 ⁽¹⁾
A9
b1 ⁽¹⁾
A8
Write
A10
A9
A8
Read
Write
Lock
Identification Identification Identification Read lock status
page
page
page
X
X
X
X
X
X
X
X
X
b7
A7
A7
0
0
b6
A6
A6
X
X
b5
A5
A5
X
X
b4
A4
A4
X
X
b3
A3
A3
A3
A3
b2
A2
A2
A2
A2
b1
A1
A1
A1
A1
b0
A0
A0
A0
A0
1. Address bits defined inside the DeviceSelect code (see Table 2).
1
X
X
see Section 4.2.5
X
X
X
X
X
Note:
A: significant address bit.
X: bit is Don’t Care.
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