STM32L053C6 Datasheet, PDF (108/132 Pages) STMicroelectronics – Reset and supply management

Electrical characteristics
STM32L053x6 STM32L053x8
I2S characteristics
Table 76. I2S characteristics⁽¹⁾
Symbol
Parameter
Conditions
Min
f_MCK
f_CK
I2S Main clock output
I2S clock frequency
-
Master data: 32 bits
Slave data: 32 bits
D_CK
I2S clock frequency duty
cycle
Slave receiver
t_v(WS)
WS valid time
Master mode
t_h(WS)
WS hold time
Master mode
t_su(WS)
WS setup time
Slave mode
t_h(WS)
WS hold time
Slave mode
t_{su(SD_MR)}
t_{su(SD_SR)}
Data input setup time
Master receiver
Slave receiver
t_{h(SD_MR)}
t_{h(SD_SR)}
Data input hold time
Master receiver
Slave receiver
t_{v(SD_ST)}
t_{v(SD_MT)}
Data output valid time
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
t_{h(SD_ST)}
t_{h(SD_MT)}
Data output hold time
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
1. Guaranteed by characterization results.
2. 256xFs maximum value is equal to the maximum clock frequency.
256 x 8K
-
-
30
-
11
6
2
0
6.5
18
15.5
-
-
18
1.5
Max
256xFs ⁽²⁾
64xFs
64xFs
70
15
-
-
-
-
-
-
-
77
8
-
-
Unit
MHz
MHz
%
ns
Note:
Refer to the I2S section of the product reference manual for more details about the sampling
frequency (Fs), f_MCK, f_CK and D_CK values. These values reflect only the digital peripheral
behavior, source clock precision might slightly change them. DCK depends mainly on the
ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of
(I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition.
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