AM79C940 Datasheet, PDF (103/144 Pages) Advanced Micro Devices – Media Access Controller for Ethernet (MACE)

AC WAVEFORMS
SCLK
(EDSEL = 0)
SCLK
(EDSEL = 1)
ADD[4:0]
R/W
CS
DBUS[15:0]
DTV
EOF
BE0-1
TC = 0
TL TH S0 S1 W0 W1 S2 S3 S0 S1 W0 W1 S2 S3 S0 S1 W0 W1 S2 S3 S0
TL TH S0 S1 W0 W1 S2 S3 S0 S1 W0 W1 S2 S3 S0 S1 W0 W1 S2 S3 S0
31
32
33
34
41
48
Word N
49
37
Word N+1
Last Byte
or Word
38
43
42
34
Host System Interface—3-Cycle Transmit FIFO/Register Write Timing
16235D-28
SCLK
(EDSEL = 0)
S2 S3 S0 S1 S2
S0 S1 S2 S3 S0
S0 S1 S2 S3
SCLK
(EDSEL = 1)
S2 S3 S0 S1 S2
EOF
44
RDTREQ
S0 S1 S2 S3 S0
40
39
Note 1
S0 S1 S2 S3
45
16235D-29
Note: Once the host detects the EOF output active from the MACE device (S2/S3 edge), if no other receive packet exists
in the RCVFIFO which meets the assert conditions for RDTREQ, the MACE device will deassert RDTREQ within 4 SCLK
cycles (S0/S1 edge). This is consistent for both 2 or 3 cycle read operations.
Host System Interface–RDTREQ Read Timing
103