TDA7407D Datasheet, PDF (10/34 Pages) STMicroelectronics – ADVANCED CAR SIGNAL PROCESSOR

TDA7407D
Table 8. ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min. Typ. Max. Unit
V_{RECT DEV} deviation dependent
rectifier Voltage ³⁾
means. with
V_MPX = 800mV
(75KHz dev.)
OVD = 11 0.5 0.9(off) 1.3 V_OP
OVD = 10 0.9 1.2 1.5 V_OP
OVD = 01 1.7 2.0 2.3 V_OP
OVD = 00 2.5 2.8 3.1 V_OP
V_{RECT FS} Fieldstrength Controlled
means. with
FSC = 11 0.5 0.9(off) 1.3
V
Rectifier Voltage ⁴⁾
V_MPX = 0mV
V_LEVEL << V_SBL
(fully mono)
FSC = 10 0.9 1.4 1.5
V
FSC = 01 1.7 1.9 2.3
V
FSC = 00 2.1 2.4 3.1
V
T_S Suppression Pulse
) _{Duration 5)}
duct(s V_RECTADJ Noise Rectifier discharge
ro ^{) adjustment 6)}
solete^{roPduct(s SRPEAK Noise Rectifier Charge}
- ^{Ob te P VADJMP Noise Rectifier adjustment}
ct(s) ^{bsole through Multipath 8)}
Signal HOLDNin Testmode
Signal PEAK in Testmode
Signal PEAK in Testmode
Signal PEAK in Testmode
BLT = 00
BLT = 10
BLT = 01
BLT = 00
NRD = 00 ⁶⁾
NRD = 01 ⁶⁾
NRD = 10 ⁶⁾
NRD = 11 ⁶⁾
PCH = 0 ⁷⁾
PCH = 1 ⁷⁾
MPNB = 00 ⁸⁾
MPNB = 01 ⁸⁾
MPNB = 10 ⁸⁾
MPNB = 11 ⁸⁾
TBD
TBD
TBD
TBD
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
38
32
25.5
22
0.3
0.8
1.3
2.0
10
20
0.3
0.5
0.7
0.9
TBD
TBD
TBD
TBD
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
µs
µs
µs
µs
V/ms
V/ms
V/ms
V/ms
mV/µs
mV/µs
V/ms
V/ms
V/ms
V/ms
du _- ^O (c) = by design/characterization functionally guaranteed through dedicated test mode structure
ro ^{0) All Thresholds are measured using a pulse with TR =2ms, THIGH = 2ms and TF = 10ms. The repetition rate must not increase the PEAK}
) _voltage.
P _t(s 1) NBT represents the Noiseblanker Byte bits D2, D0 for the noise blanker trigger threshold
2) NAT represents the Noiseblanker Byte bit pair D4, D3 for the noise controlled triggeradjustment
te ^{c 3) OVD represents the Noiseblanker Byte bit pair D7, D6 for the over deviation detector}
le ^{u 4) FSC represents the Fieldstrength Byte bit pair D1, D0 for the fieldstrength control}
d _{5) BLT represents the Speaker RR Byte bit pair D7, D6 for the blanktime adjustment}
so ^{ro 6) NRD represents the Configuration-Byte bit pair D1, D0 for the noise rectifier discharge-adjustment}
7) PCH represents the Stereodecoder-Byte bit D5 for the noise rectifier charge-current adjustment
b P 8) MPNB represents the HighCut-Byte bit D7 and the Fieldstrength-Byte D7 for the noise rectifier multipath adjustment
O _{te Figure 4.}
sole _VIN
Ob ^VOP
DC
D97AU636
TR THIGH
TF
Time
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