STI5500 Datasheet, PDF (10/11 Pages) STMicroelectronics – SET TOP BOX / DVD BACKEND DECODER WITH INTEGRATED HOST PROCESSOR

STi5500
CONFIDENTIAL ^{III - INTERNAL CIRCUIT DESCRIPTION (continued)}
The ST20 arbitor can make two types of requests
into SDRAM, a single word access (32-bits) or a
burst access of 4 x 32-bit words. The following table
For program specific information (EPG etc) this
data my be sent to an external buffer in SDRAM or
a memory on the external ST20 EMI.
summerizes the different types of accesses by
source and destination (see Table 1).
In a DVD system the incoming sector stream data
would be sent, using the DMA in the front end
Data is moved around the device using a number interface to a track buffer which could be either in
of general purpose DMA engines which are kicked external DRAM off the ST20 EMI or in shared
off by the CPU at a certain address and are then SDRAM. This is automatic and needs no CPU
autonomous. In a typical application data will arrive intervention appart from an initial configuration.
via the front-end interface (a transport stream in a The track buffer is then parsed in software and two
set-top application or a program / sector stream in general purpose DMAs can be used to transfer
a DVD application (see Table 1).
blocks of data from the track buffer to the com-
The link interface has a built in programmable DMA
multichannel engine which can be used to direct
the data to any memory or memory mapped periph-
pressed data FIFOs to be decoded. In a set-top box
application a transport stream can be split by pid
into many component streams.
eral. In the case of a set-top application a DMA The video/audio streams would be directly sent to
destination can be defined for each pid so for the CD fifos using a non-incremental DMA transfer.
audio/video (PES) data this destination would be Other streams such as EPG data can be stored as
the compressed data FIFOs which are mapped into a circular buffer in another memory space using an
the ST20 memory system at specific addresses. incremental DMA.
Table 1
Source
CPU
Caches
Link Interface
SMI/SDRAM
Single Word
Burst
Burst/Single
ST20 EMI
Single Word
Burst
Burst/Single
Internal SRAM
Single Word
Single Word
Single
Compressed Data/Reg. Port
Single Word
n/a
Single
DMA Engines
Video Decoder
Audio Decoder
Single
Large Bursts
Large Bursts
Single
n/a
n/a
Single
n/a
n/a
Single
n/a
n/a
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