M68AR512D Datasheet, PDF (10/19 Pages) STMicroelectronics – 8 Mbit 512K x16 1.8V Asynchronous SRAM

M68AR512D
Table 7. Read and Standby Mode AC Characteristics
Symbol
Parameter
M68AR512D
Unit
70
t_AVAV
Read Cycle Time
Min
70
ns
t_AVQV
Address Valid to Output Valid
Max
70
ns
t_AXQX ⁽¹⁾ Data hold from address change
Min
5
ns
t_BHQZ ^{(2, 3)} Upper/Lower Byte Enable High to Output Hi-Z
Max
25
ns
t_BLQV
Upper/Lower Byte Enable Low to Output Valid
Max
70
ns
t_BLQX ⁽¹⁾ Upper/Lower Byte Enable Low to Output Transition
Min
5
ns
t_EHQZ ^{(2, 3)} Chip Enable High to Output Hi-Z
Max
25
ns
t_ELQV
Chip Enable Low to Output Valid
Max
70
ns
t_ELQX ⁽¹⁾ Chip Enable Low to Output Transition
Min
5
ns
t_GHQZ ^{(2, 3)} Output Enable High to Output Hi-Z
Max
25
ns
t_GLQV Output Enable Low to Output Valid
Max
35
ns
t_GLQX ⁽¹⁾ Output Enable Low to Output Transition
Min
5
ns
t_PD ⁽⁴⁾
Chip Enable High to Power Down
Max
0
ns
t_PU ⁽⁴⁾
Chip Enable Low to Power Up
Min
70
ns
Note: 1. Test conditions assume transition timing reference level = 0.3V_CCQ to 0.7V_CCQ.
2. At any given temperature and voltage condition, t_GHQZ is less than t_GLQX, t_BHQZ is less than t_BLQX and t_EHQZ is less than t_ELQX for
any given device.
3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
4. Tested initially and after any design or process changes that may affect these parameters.
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