LNBH26PQR Datasheet, PDF (10/38 Pages) STMicroelectronics – Dual LNBS supply and control IC with step-up and I²C interface

Application information (valid for each section A/B)
LNBH26
2.17
PNG: input voltage minimum detection
When input voltage (V_CC pin) is lower than LPD (low power diagnostic) minimum thresholds,
the PNG I²C bit is set to “1” and the FLT pin is set low. Refer to Table 3 for threshold details.
2.18
ISW: inductor switching current limit
In order to allow low saturation current inductors to be used, the maximum DC-DC inductor
switching current limit threshold can be set by means of one I²C bit per section (ISW). Two
values are available: 2.5 A typ. (with ISW = 1) and 4 A typ. (with ISW = 0).
2.19
COMP: boost capacitor ESR
The DC-DC converter compensation loop can be optimized in order to work well with high or
low ESR capacitors (on the V_UP pin). For this purpose, one I²C bit in the DATA4 register
(COMP) can be set to “1” or “0”. It is recommended to reset this bit to “0” unless using high
ESR capacitors.
2.20
10/38
OLF: overcurrent and short-circuit protection and diagnostic
In order to reduce the total power dissipation during an overload or a short-circuit condition,
each section of the device is provided with a dynamic short-circuit protection. It is possible to
set the short-circuit current protection either statically (simple current clamp) or dynamically
by the corresponding PCL bit of the I²C DATA3 register. When the PCL (pulsed current
limiting) bit is set lo LOW, the overcurrent protection circuit works dynamically: as soon as
an overload is detected, the output current is provided for T_ON time (90 ms or 180 ms typ.,
according to the corresponding TIMER bit programmed in the DATA3 register) and after that,
the output is set in shutdown for a T_OFF time of typically 900 ms. Simultaneously, the
corresponding diagnostic OLF I²C bit of the STATUS1 register is set to “1” and the FLT pin is
set to low level. After this time has elapsed, the involved output is resumed for a time T_ON. At
the end of T_ON, if the overload is still detected, the protection circuit cycles again through
T_OFF and T_ON. At the end of a full T_ON in which no overload is detected, normal operation is
resumed and the OLF diagnostic bit is reset to LOW after register reading is done. Typical
T_ON +T_OFF time is 990 ms (if TIMER=0) or 1080 ms (if TIMER=1) and is determined by an
internal timer. This dynamic operation can greatly reduce the power dissipation in short-
circuit condition, still ensuring excellent power-on startup in most conditions. However, there
may be some cases in which a highly capacitive load on the output can cause a difficult
startup when the dynamic protection is chosen. This can be solved by initiating any power
startup in static mode (PCL=1) and then, switching to dynamic mode (PCL=0) after a
chosen amount of time, depending on the output capacitance. Also in static mode, the
diagnostic OLF bit goes to “1” (and the FLT pin is set to low) when the current clamp limit is
reached and returns LOW when the overload condition is cleared and register reading is
done.
After the overload condition is removed, normal operation can be resumed in two ways,
according to the OLR I²C bit on the DATA4 register.
If OLR=1, all VSEL bits corresponding to the involved section are reset to “0” and the LNB
section output (V_OUT pin) is disabled. To re-enable the output stage, the VSEL bits must be
set again by the microprocessor and the OLF bit is reset to “0” after a register reading
operation.
Doc ID 022771 Rev 1