E-L9823 Datasheet, PDF (10/19 Pages) STMicroelectronics – Octal low-side driver for bulb, resistive and inductive loads with serial input control, output protection and diagnostic

Electrical specifications
L9823
Table 5.
Symbol
Electrical characteristics (continued)
Parameter
Test condition
Min.
Typ. Max. Unit
C_OUT Output capacitance
Outputs short circuit protection
V_OUT = 16 V; f = 1 MHz
-
-
300 pF
I_SCB Overcurrent shutoff threshold
I_{OUT LIM} Short circuit current limitation
t_{dly SCB} Short circuit shutdown delay
Diagnostics
SFPD = Low, V_OUT ≥ V_DG
-
SFPD = Low, V_OUT ≥ V_DG
CSB = 50% to
I_OUT ≤ 1/2 I_{OUT LIM}
0.5
1.6
2.5 A
0.5
1.6
2.5 A
70
150
250 µs
V_DG Diagnostic threshold voltage
I_{OUT OL}
Open load detection sink
current
-
V_out = V_DG
Output programmed OFF
t_{dly SFPD}
Diagnostic detection filter time
SFPD = Low, V_OUT ≥ V_DG
CSB = 50% to valid data at SO
0.5·V_DD 0.55·V_DD 0.6·V_DD V
30
60
100 µA
70
150
250 µs
Outputs timing
t_don Turn-on delay
t_doff Turn-off delay
dV_on/dt Turn-on voltage slew-rate
dV_off/dt Turn-off voltage slew-rate
dV_off Turn-off voltage clamp slew-
clamp/dt ^rate
CSB = 50% to R_L = 50 Ω
V_OUT = 0.9 V_bat, V_bat = 16 V
CSB = 50% to R_L = 50 Ω
V_OUT = 0.1·V_bat, V_bat = 16 V
90% to 30% of V_bat;
R_L = 50 Ω; V_bat = 16 V
30% to 90% of V_bat;
R_L = 50 Ω; V_bat = 16 V
30% to 80% of V_{OUT clamp}
R_L = 500 Ω
Serial diagnostic link (Load capacitor at SO = 200 pF)
-
-
20 µs
-
-
20 µs
0.7
2.1
3.5 V/µs
0.7
2.1
3.5 V/µs
0.7
2.1
5.5 V/µs
f_sclk Clock frequency
50% duty cycle
3
t_clh Minimum time SCLK = HIGH -
160
t_cll Minimum time SCLK = LOW -
160
Propagation delay
t_{pcld SCLK to data at SO valid}
4.9V ≤ V_DD ≤ 5.1V
-
t_csdv
CSB = LOW to data at SO
active
-
-
t_sclch SCLK low before CSB low
Setup time SCLK to CSB change
H/L
100
t_hclcl
SCLK change L/H after CSB = Setup time CSB to SCLK change
Low
L/H
100
t_scld SI input setup time
SCLK change H/L after SI data
valid
20
-
- MHz
-
-
ns
-
-
ns
-
100 ns
-
100 ns
-
-
ns
-
-
ns
-
-
ns
10/19
Doc ID 7791 Rev 5