AN3342 Datasheet, PDF (10/39 Pages) STMicroelectronics – Getting started with STM8TL5xxx

Reset control
4
Reset control
AN3342
4.1
4.1.1
10/39
Reset management overview
The reset pin is a 3.3 V bidirectional I/O (supplied by V_DDIO). After startup it can be
programmed by software to be used as a general purpose output.
Its output buffer driving capability is fixed to Iol_MIN = 2 mA @ 0.45 V in the 1.65 V to 3.6 V
range which includes a ~40 k pull-up. Output buffer is reduced to the n-channel MOSFET
(NMOS). The receiver includes a glitch filter, whereas the output buffer includes a 20 µs
delay.
There are many reset sources, including:
● External reset through the NRST pin
● Power-on reset (POR): During power-on, the POR keeps the device under reset until
the supply voltage (V_DD) reach the right voltage level.
● Independent watchdog reset (IWDG)
● Window watchdog reset (WWDG), featuring also software reset.
● SWIM reset: An external device connected to the SWIM interface can request the
SWIM block to generate a microcontroller reset.
● Illegal opcode reset: If a code to be executed does not correspond to any opcode or
prebyte value, a reset is generated.
Figure 3 shows a simplified functional I/O reset schematic.
Figure 3. Reset management
STM8TL5xxx
External
reset circuit
NRST
100 nF
V_{DD_IO}
R_PU
(typ 40 kΩ)
Filter
Pulse
generator
(min 20 µs)
Delay
System reset
Illegal op code reset
IWDG/WWDG/software reset
SWIM reset
POR reset
MS18949V2
Output characteristics
● A valid pulse on the pin is guaranteed with a  20 ns pulse duration on the internal
output buffer.
● After a valid pulse is recognized, a pulse on the pin of at least 20 µs is guaranteed
starting from the falling edge of A (output of the OR between the different reset
sources).
Doc ID 18461 Rev 3