TS555CDT Datasheet, PDF (1/20 Pages) STMicroelectronics – Low power single CMOS timer

TS555
Low power single CMOS timer
Features
■ Very low power consumption:
110 µA typ at V_CC = 5 V
90 µa typ at V_CC = 3 V
■ High maximum astable frequency of 2.7 MHz
■ Pin-to-pin functionally-compatible with bipolar
NE555
■ Wide voltage range: +2 V to +16 V
■ Supply current spikes reduced during output
transitions
■ High input impedance: 10¹² Ω
■ Output compatible with TTL, CMOS and logic
MOS
Description
The TS555 is a single CMOS timer with a very
low consumption:
(I_cc(TYP) TS555 = 110 µA at V_CC = +5 V versus
I_cc(TYP) NE555 = 3 mA),
and high frequency:
(f_f(max.) TS555 = 2.7 MHz versus
f_(max) NE555 = 0.1 MHz).
Timing remains accurate in both monostable and
astable mode.
The TS555 provides reduced supply current
spikes during output transitions, which enable the
use of lower decoupling capacitors compared to
those required by bipolar NE555.
With the high input impedance (10¹²Î©), timing
capacitors can also be minimized.
N
DIP8
(Plastic package)
D
SO8
(Plastic micropackage)
P
TSSOP8
(Thin shrink small outline package)
Pin connections
(top view)
GND 1
Trigger 2
Output 3
Reset 4
8 V_CC
7 Discharge
6 Threshold
5
Control
Voltage
November 2008
Rev 2
1/20
www.st.com
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