TN0024 Datasheet, PDF (1/11 Pages) STMicroelectronics – Power supply HOLD-UP time

TN0024
Technical note
Power supply HOLD-UP time
Introduction
A warning signal at a time period is often requested from a power supply for the load to
complete housekeeping chores before the output voltage drops out of regulation. A circuit
to monitor AC input voltage and a bulk capacitor of sufficient size are often used to meet
these requirements.
The HOLD-UP time of an off line, high frequency power supply can be defined as the time
required for the output voltage to remain within regulation after the AC input voltage is
removed. It is commonly expressed in ms from a specific input voltage, which is usually less
than the nominal AC input voltage, and at a specific output power. The power supply is
designed to regulate output voltage at the DC bulk voltage which is reached after the HOLD-
UP time.
If a HOLD-UP time is required, there are tradeoffs with respect to the power supply design
input voltage and regarding the size of bulk capacitors. Often the major part of the power
supply design, on the primary side, depends on the lowest DC bulk voltage after the HOLD-
UP time in which the power supply can operate.
This document presents a comparison between lab data, P-Spice simulation and MathCAD
analysis of the same high frequency off line power supply. The power supply is a
VIPer53DIP-E demo board with a universal 85 to 264 VAC input voltage and a 12 V output
voltage with a 2 A load. The inrush resistor, R1, is 3 Ω and the common mode inductor, L1,
is about 2.5 Ω. The bulk capacitor, C2, is 68 µF and measures about 60 µF. The
requirement is for a 10ms HOLD-UP time, an AC voltage at turn off of 110 V_AC and the
power supply is designed to operate at an input voltage of 80 V_DC.
February 2007
Rev 1
1/11
www.st.com