STW51000 Datasheet, PDF (1/8 Pages) STMicroelectronics – SUPER INTEGRATED DSP ENGINE

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STW51000
SUPER INTEGRATED DSP ENGINE
DATA BRIEF
1 Product Features
■ Super Integrated SoC including 2 x ST140 quad
MAC DSP engines running at 600MHz and 1 x
ARM926 Micro Controller running at 300MHz
■ Double Quad-MAC units
■ Double Quad-ALU (32 and 40-bit)
■ 4800 MMacs/s - 29000 Mops - 7500 Mips
■ Convolutional Decoder Engine:
– 256 x 12.2 kpbs AMR voice users
– Programmable Code Parameters to support
multi-standards (W-CDMA, TD-SCDMA,
CDMA2000 and EDGE)
■ Turbo Decoder Engine:
– 28 x 384 kbps (8 iterations)
– Programmable Code Parameters to support
multi-standards (W-CDMA, TD-SCDMA and
CDMA2000)
– Includes CRC Processing
– Hardware Interleaver with multi-standard
support
■ Two 32-channel DMA Engines
■ 16Mbit Central Memory shared among DSPs,
µC and DMA Engines
■ One 32-bit External Memory Controller
■ One external Master Interface
■ One 32-bit Communication Interface
■ Two Multi-Channel Serial Ports
■ Two Ethernet MAC
■ One 16-bit UTOPIA Level 2 Interface
■ 32-bit General Purpose I/Os
■ Two 32-bit Timers
■ Programmable PLL Clock Generator
■ IEEE-1149.1 (JTAG)
■ Development tools available
■ Baseband modem SW deliverables available
2 ST140 Features
■ 32-bit Load/Store Architecture
■ 16-bit, 32-bit or 128-bit (SLIW) Instruction Set for
high performance / high code density trade off
Figure 1. Package
PBGA/HSP-569
Table 1. Order Codes
Part Number
STW51000AT
Package
PBGA/HSP-569
■ Conditional Instructions to reduce code size and
overhead
■ Built-in Coprocessor Interfaces for highly
optimized Instruction Definition
■ Compiler Friendly Instruction Set for high
performance critical DSP Routines directly from
C
■ 8, 16, 32 and 40-bit Data Support
■ Circular and bit-reversed Data addressing
modes
■ 32x16 bit Multiplier eases floating point to fixed
point conversion
■ 8-bit Overflow protection
■ Bit Manipulation
■ Normalization, Saturation
■ Zero Overhead Loops
■ 32Kbytes L1 Program Cache and 64Kbytes L1
Data Cache
3 ARM926 Features
■ 32/16-bit RISC Architecture
■ 32-bit ARM Instruction Set for maximum
performance and flexibility
■ 16-bit Thumb Instruction set for high code
density
■ Built-in Memory Management Unit for OS
Support
■ 32Kbytes L1 Program Cache
■ 16KBytes L1 Data Cache
April 2005
This is preliminary information on a new product now in development. Details are subject to change without notice.
Rev. 2
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