STV7733 Datasheet, PDF (1/28 Pages) STMicroelectronics – 320 output dot-matrix display driver

STV7733
320 output dot-matrix display driver
Preliminary Data
Features
s High-voltage, row/column driver IC
s 320, tri-level (high-voltage, medium voltage
and ground) power outputs:
– capable of operating at 90V, absolute max.
– capable of sinking or sourcing 2mA
– Hi-Z
s Logic supply range: 2.5V to 3.3V
s Slim shape die for COG, COF and TCP
solutions
s Interface:
– four dual (2-bit) input serial buses:
DB_A[1:2], DB_B[1:2], DB_C[1:2] and DB_D[1:2]
operating at shift clock frequency of
10MHz, max.
– three control inputs: shift clock direction
(DIR), chip select (/CS) and data latch
(/DL)
– two “all output” stage control inputs: AOC1
and AOC2
s Power supplies:
– high-voltage for power outputs: 90V, max.
– logic supply suitable for battery powered
applications: 2.5V, min.
Description
The STV7733 device is a low-power,
controller/driver IC for dot-matrix displays. Data is
encoded on two bits to select one of four possible
output states: high level, medium level, ground or
high impedance (Hi-Z).
Inputs AOC1 and AOC2 control the all output
stages simultaneously to select one of five
possible configurations: high level, medium level,
ground, Hi-Z or data through.
Except for the data through mode, the
configuration selected by AOC1 and AOC2 is
applied to all outputs at the same time.
The STV7733 communicates with the host
controller through an 8-bit parallel interface. The
input data bus is organized as four, 2 x 80-bit shift
registers operating in parallel at a maximum clock
frequency of 10MHz.
Logic inputs are LVCMOS compatible.
The STV7733 is available in bumped die form.
Bumped die can be assembled in either a TCP or
COG module.
Figure 1. Block diagram
DIR
/CS SCLK
VDD
DB_A1
DB_A2
DBB1
DBB2
DB_C1
DB_C2
DB_D1
DB_D2
/DL
AOC1
AOC2
POE
HVDD
MVDD
VSSP
2 x 80-bit shift register
2 x 80-bit shift register
2 x 80-bit shift register
2 x 80-bit shift register
Q1 Q2 Q3 Q4
Q320
2 x 320-bit latch
Output control
Tri-level output buffer stage
VSSL
STBTEST
OE
VSSS
HVDD
MVDD
VSSP
OUT1 OUT2
OUT320
May 2007
Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
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