STV7622 Datasheet, PDF (1/32 Pages) STMicroelectronics – 192 output plasma display panel data driver

STV7622
192 output plasma display panel data driver
Preliminary Data
Features
s 192 high-voltage outputs
s Output pad placements: I-shape
s 90V absolute maximum supply
s EMI control features:
– SmartSlope
– ConstantSlope
– Spread Spectrum Jitter (SSJ)
s Configurable data bus:
– 3, 6 or 2 × 3 bits
– TTL and LVCMOS compatible
– RSDS mode
– Single- or dual-edge clocking mode
– 60MHz clock frequency
s 3.3/5V CMOS logic compatible
s - 60/+24mA source/sink output current
capability
s BCD Process
s Packaging according to customer request:
wafer, die, bumped die/wafer, TCP or COF
Description
The STV7622 is a data driver for Plasma Display
Panels (PDP) designed in the ST’s proprietary
BCD high-voltage technology.
It controls up to 192 outputs via an input data bus
(3, 6 or 2 × 3-bits wide) operating at up to 60MHz.
This large number of outputs reduces the number
of connections between the controller board and
the data driver ICs.
The STV7622 contains a new logic input stage
that minimizes EMI resulting from the
transmission of high speed TTL or LVCMOS data
and clock signals. This new input stage is RSDS
compliant. It enables increasing the operating
frequency without compromising noise immunity.
The input data bus is configured by dedicated
input pins:
q BS1 and BS2: bus width select (3, 6,
2 × 3 bits or RSDS mode)
q DIR input: shift register loading direction
The STV7622 output stage integrates several ST
patented functions aimed at reducing EMI without
compromising addressing speed or performance
of the PDP modules.
These functions mainly consist of:
q SmartSlope: controls the output falling edge
speed /shape
q ConstantSlope: controls the output rising
edge speed
q Spread Spectrum Jitter (SSJ): controls the
spread of the output rising edge
The STV7622 is powered by a separate 70V
supply for the high-voltage outputs and a 5V
supply for the logic. All command input levels are
5V CMOS as well as 3.3V compatible.
Figure 1. Block diagram
BS1 BS2 DIR
CLK1 CLK2 VDD
DB1
DB2
DB3
DB4
DB5
DB6
/STB1
/STB2
Data decoding
Q1 Q2 Q3 Q4
32-bit Shift register
32-bit Shift register
32-bit Shift register
32-bit Shift register
32-bit Shift register
32-bit Shift register
Latch
Q192
/BLK
Output control / EMI control
POC
Output buffer stage
VSSLOG
TEST1
TEST2
VREF
10nF
VCC
RS1
RS2
FS1
FS2
VPP
VSSP
VSSSUB
OUT1 OUT2 OUT3 …..
…. OUT192
May 2007
Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/32
www.st.com
32