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STV6110A Datasheet, PDF (1/5 Pages) STMicroelectronics – 8PSK/QPSK low-power 3.3 V satellite tuner IC | |||
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STV6110A
8PSK/QPSK low-power 3.3 V satellite tuner IC
Data Brief
Features
â RF to baseband 8PSK/QPSK direct conversion
â Single 3.3 V DC supply
â Input frequency range 950 MHz to 2150 MHz
â Supports 1 to 45 Msymbol/s
â On-chip RF loop-through
â Fully integrated PLL frequency synthesizer for
DVB-S2 (including loop filter)
â Extremely low phase noise compliant with
DVB-S2 requirements
â Low external component count
â Low power consumption
â Flexible crystal frequency output to drive the
demodulator IC
â Continuously variable gain: 0 to 65 dB
â Additional and programmable gain on
baseband amplifier: 0 to 16 dB
â Programmable 5- to 36-MHz cut-off frequency
(butterworth 5th-order baseband filters)
â Compatible with 5-V and 3.3 V I2C bus
Description
The STV6110A satellite tuner is a direct-
conversion (zero IF) receiver dedicated to digital
TV broadcasting.
On the RF input is a low noise amplifier (LNA),
with buffer to supply the RF output for
loop-through, and a continuously variable gain
LNA to ensure an optimal signal level for the two
mixers. Each mixer, which down-converts the
signal to baseband, is followed by a low-pass filter
and amplifier. The baseband gain can be varied
by programming a register via the I2C bus.
The LO signals are provided by an integrated PLL
which contains an on-chip voltage controlled
oscillator (VCO) meeting stringent phase noise
requirements. The PLL loop filter is integrated.
The LO frequencies are programmable.
The comparison frequency for the phase-
frequency detector (PFD) is generated by dividing
the crystal oscillator reference frequency. The
crystal frequency can be from 16 MHz to 32 MHz
depending on application.
RF_IN
AGC
XTAL_IN
XTAL_INN
XTAL_OUT
PLL, dividers
Amplifier
DC offset compensation
I2C bus interface
RF_OUT
IP
IN
QP
QN
SCL
SDA
August 2008
Rev 1
For further information contact your local STMicroelectronics sales office.
1/5
www.st.com
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