STPCCONSUMER-II Datasheet, PDF (1/93 Pages) STMicroelectronics – X86 Core PC Compatible Information Appliance System-on-Chip

STPC^® CONSUMER-II
X86 Core PC Compatible Information Appliance System-on-Chip
s POWERFUL x86 PROCESSOR
s 64-BIT SDRAM UMA CONTROLLER
s VGA & SVGA CRT CONTROLLER
s 135 MHz RAMDAC
s 2D GRAPHICS ENGINE
s VIDEO INPUT PORT
s VIDEO PIPELINE
- UP-SCALER
- VIDEO COLOUR SPACE CONVERTER
- CHROMA & COLOUR KEY SUPPORT
s TV OUTPUT
- THREE-LINE FLICKER FILTER
- ITU-R 601/656 SCAN CONVERTER
- NTSC / PAL COMPOSITE, RGB, S-VIDEO
s PCI MASTER / SLAVE / ARBITER
s ISA MASTER / SLAVE
s OPTIONAL 16-BIT LOCAL BUS INTERFACE
s EIDE CONTROLLER
s I²C INTERFACE
s IPC
- DMA CONTROLLER
- INTERRUPT CONTROLLER
- TIMER / COUNTERS
s POWER MANAGEMENT UNIT
s JTAG IEEE1149.1
DESCRIPTION
The STPC Consumer-II integrates a standard 5th
generation x86 core, a Synchronous DRAM
controller, a graphics subsystem, a video pipeline,
and support logic including PCI, ISA, and IDE
controllers to provide a single consumer
orientated PC compatible subsystem on a single
device.
The device is based on a tightly coupled Unified
Memory Architecture (UMA), sharing memory
between the CPU, the graphics and the video.
The STPC Consumer-II is packaged in a 388
Plastic Ball Grid Array (PBGA).
STPC _{Consumer II}
PBGA388
Figure 0-1. Logic Diagram
Host x86
I/F Core
PCI
PCI Bus
m/s
PMU
LB
CTR
IPC
ISA
m/s
PCI
m/s
IDE
I/F
ISA Bus
Local Bus
Video
Pipeline
SVGA
CRTC
GE
VIP
C Key
K Key
LUT
Cursor
Monitor
TVO
Encoder ^TV
SDRAM
CTRL
JTAG
Release 1.5 - January 29, 2002
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