STP9NB50 Datasheet, PDF (1/9 Pages) STMicroelectronics – N-CHANNEL 500V - 0.75 ohm - 8.6 A TO-220/TO-220FP PowerMesh MOSFET

STP9NB50
STP9NB50FP
N-CHANNEL 500V - 0.75 Ω - 8.6 A TO-220/TO-220FP
PowerMesh™ MOSFET
TYPE
V_DSS
R_DS(on)
I_D
STP9NB50
500 V < 0.85 Ω 8.6 A
STP9NB50FP
500 V < 0.85 Ω 4.9 A
s TYPICAL R_DS(on) = 0.75 Ω
s EXTREMELY HIGH dv/dt CAPABILITY
s 100% AVALANCHE TESTED
s VERY LOW INTRINSIC CAPACITANCES
s GATE CHARGE MINIMIZED
DESCRIPTION
Using the latest high voltage MESH OVERLAY™
process, STMicroelectronics has designed an ad-
vanced family of power MOSFETs with outstanding
performances. The new patent pending strip layout
coupled with the Company’s proprieraty edge termi-
nation structure, gives the lowest R_DS(on) per area,
exceptional avalanche and dv/dt capabilities and
unrivalled gate charge and switching characteris-
tics.
APPLICATIONS
s HIGH CURRENT, HIGH SPEED SWITCHING
s SWITH MODE POWER SUPPLIES (SMPS)
s DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
3
2
1
TO-220
3
2
1
TO-220FP
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
V_DS
V_DGR
V_GS
I_D
I_D
I_DM (q)
P_TOT
Drain-source Voltage (V_GS = 0)
Drain-gate Voltage (R_GS = 20 kΩ)
Gate- source Voltage
Drain Current (continuos) at T_C = 25°C
Drain Current (continuos) at T_C = 100°C
Drain Current (pulsed)
Total Dissipation at T_C = 25°C
Derating Factor
dv/dt (1) Peak Diode Recovery voltage slope
V_ISO
Insulation Withstand Voltage (DC)
T_stg
Storage Temperature
T_j
Max. Operating Junction Temperature
(•)Pulse width limited by safe operating area
May 2000
Value
STP9NB50 STP9NB50FP
500
500
±30
8.6
4.9
5.4
3.1
34.4
34.4
125
40
1
0.32
4.5
4.5
-
2000
–65 to 150
150
(1)I_SD<9A, di/dt<200A/µ, V_DD<V_(BR)DSS,TJ<T_JMAX
Unit
V
V
V
A
A
A
W
W/°C
V/ns
V
°C
°C
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