STP9NA50 Datasheet, PDF (1/10 Pages) STMicroelectronics – N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR

STP9NA50
STP9NA50FI
N - CHANNEL ENHANCEMENT MODE
FAST POWER MOS TRANSISTOR
TYPE
ST P 9NA 50
ST P 9NA 50 F I
VDSS
500 V
500 V
R DS( on)
< 0.8 Ω
< 0.8 Ω
ID
8.8 A
5A
s TYPICAL R_DS(on) = 0.7 Ω
s ± 30V GATE TO SOURCE VOLTAGE RATING
s 100% AVALANCHE TESTED
s REPETITIVE AVALANCHE DATA AT 100^oC
s LOW INTRINSIC CAPACITANCES
s GATE GHARGE MINIMIZED
s REDUCED THRESHOLD VOLTAGE SPREAD
DESCRIPTION
This series of POWER MOSFETS represents the
most advanced high voltage technology. The
optimized cell layout coupled with a new
proprietary edge termination concur to give the
device low R_DS(on) and gate charge, unequalled
ruggedness and superior switching performance.
APPLICATIONS
s HIGH CURRENT, HIGH SPEED SWITCHING
s SWITCH MODE POWER SUPPLIES (SMPS)
s DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
ABSOLUTE MAXIMUM RATINGS
Symbol
P ar amete r
V_{D S}
V_{DG R}
Drain-source Voltage (V_GS = 0)
Drain-gate Voltage (R_{G S} = 20 kΩ)
VGS
I_D
I_D
ID M(•)
Ptot
Gate-source Voltage
Drain Current (continuous) at T _c = 25 ^oC
Drain Current (continuous) at T _c = 100 ^oC
Drain Current (pulsed)
Total Dissipation at Tc = 25 ^oC
Derating Factor
VISO Insulation Withstand Voltage (DC)
Tstg Storage Temperature
T_j
Max. Operating Junction Temperature
(•) Pulse width limited by safe operating area
February 1994
3
2
1
TO-220
3
2
1
ISOWATT220
INTERNAL SCHEMATIC DIAGRAM
Val ue
STP9NA50
STP9NA50FI
500
500
± 30
8.8
5
5.5
3.1
35
35
125
45
1
0. 36

2000
-65 to 150
150
Unit
V
V
V
A
A
A
W
W/^oC
V
o_C
o_C
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