STP8NC70Z Datasheet, PDF (1/13 Pages) STMicroelectronics – N-CHANNEL 700V - 0.90ohm - 6.8A TO-220/FP/D2PAK/I2PAK Zener-Protected PowerMESH™III MOSFET

STP8NC70Z - STP8NC70ZFP
STB8NC70Z - STB8NC70Z-1
N-CHANNEL 700V - 0.90Ω - 6.8A TO-220/FP/D²PAK/I²PAK
Zener-Protected PowerMESH™III MOSFET
TYPE
V_DSS
R_DS(on)
I_D
STP8NC70Z/FP
700V
< 1.2 Ω
6.8 A
STB8NC70Z/-1
700V
< 1.2 Ω
6.8 A
s TYPICAL R_DS(on) = 0.9 Ω
s EXTREMELY HIGH dv/dt AND CAPABILITY
GATE-TO- SOURCE ZENER DIODES
s 100% AVALANCHE TESTED
s VERY LOW GATE INPUT RESISTANCE
s GATE CHARGE MINIMIZED
DESCRIPTION
The third generation of MESH OVERLAY™ Power
MOSFETs for very high voltage exhibits unsurpassed
on-resistance per unit area while integrating back-to-
back Zener diodes between gate and source. Such ar-
rangement gives extra ESD capability with higher rug-
gedness performance as requested by a large variety
of single-switch applications.
APPLICATIONS
s SINGLE-ENDED SMPS IN MONITORS,
COMPUTER AND INDUSTRIAL APPLICATION
s WELDING EQUIPMENT
TO-220
3
1
D²PAK
3
2
1
TO-220FP
123
I²PAK
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
V_DS
Drain-source Voltage (V_GS = 0)
V_DGR
Drain-gate Voltage (R_GS = 20 kΩ)
V_GS
Gate- source Voltage
I_D
Drain Current (continuous) at T_C = 25°C
I_D
Drain Current (continuous) at T_C = 100°C
I_DM (q) Drain Current (pulsed)
P_TOT
Total Dissipation at T_C = 25°C
Derating Factor
I_GS
Gate-source Current (DC)
V_ESD(G-S) Gate source ESD(HBM-C=100pF, R=15KΩ)
dv/dt(1) Peak Diode Recovery voltage slope
V_ISO
Insulation Winthstand Voltage (DC)
T_stg
Storage Temperature
T_j
Max. Operating Junction Temperature
(•)Pulse width limited by safe operating area
December 2002
Value
Unit
STP(B)8NC70Z(-1) STP8NC70ZFP
700
V
700
V
± 25
V
6.8
6.8(*)
A
4.3
4.3(*)
A
27
27(*)
A
135
40
W
1.08
0.32
W/°C
±50
mA
3
KV
3
V/ns
--
2000
V
–65 to 150
°C
150
°C
(1)ISD ≤6.8A, di/dt ≤100A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX
.^{(*)Pulse width Limited by maximum temperature allowed} 1/13