STP7NC70Z Datasheet, PDF (1/13 Pages) STMicroelectronics – N-CHANNEL 700V - 1.1ohm - 6A TO-220/FP/D2PAK/I2PAK Zener-Protected PowerMESH™III MOSFET

STP7NC70Z - STP7NC70ZFP
STB7NC70Z - STB7NC70Z-1
N-CHANNEL 700V - 1.1Ω - 6A TO-220/FP/D²PAK/I²PAK
Zener-Protected PowerMESH™III MOSFET
TYPE
V_DSS
R_DS(on)
I_D
STP7NC70Z/FP
700V < 1.38Ω
6A
STB7NC70Z/-1
700V < 1.38Ω
6A
s TYPICAL R_DS(on) = 1.1Ω
s EXTREMELY HIGH dv/dt AND CAPABILITY GATE
TO - SOURCE ZENER DIODES
s 100% AVALANCHE TESTED
s VERY LOW GATE INPUT RESISTANCE
s GATE CHARGE MINIMIZED
DESCRIPTION
The third generation of MESH OVERLAY™ Power
MOSFETs for very high voltage exhibits unsurpassed
on-resistance per unit area while integrating back-to-
back Zener diodes between gate and source. Such ar-
rangement gives extra ESD capability with higher rug-
gedness performance as requested by a large variety
of single-switch applications.
TO-220
3
1
D²PAK
3
2
1
TO-220FP
I²PAK^{1 2 3}
(Tabless TO-220)
APPLICATIONS
s SINGLE-ENDED SMPS IN MONITORS,
COMPUTER AND INDUSTRIAL APPLICATION
s WELDING EQUIPMENT
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
V_DS
Drain-source Voltage (V_GS = 0)
V_DGR
Drain-gate Voltage (R_GS = 20 kΩ)
V_GS
Gate- source Voltage
I_D
Drain Current (continuous) at T_C = 25°C
I_D
Drain Current (continuous) at T_C = 100°C
I_DM (1) Drain Current (pulsed)
P_TOT
Total Dissipation at T_C = 25°C
Derating Factor
I_GS
Gate-source Current
V_ESD(G-S) Gate source ESD(HBM-C=100pF, R=15KΩ)
dv/dt
Peak Diode Recovery voltage slope
V_ISO
Insulation Withstand Voltage (DC)
T_stg
Storage Temperature
T_j
Max. Operating Junction Temperature
(•)Pulse width limited by safe operating area
May 2003
Value
Unit
STP(B)7NC70Z(-1) STP7NC70ZFP
700
V
700
V
± 25
V
6
6(*)
A
3.7
3.7(*)
A
24
24
A
125
40
W
1
0.32
W/°C
±50
mA
3
KV
3
V/ns
--
2000
V
–65 to 150
°C
150
°C
(1)ISD ≤6A, di/dt ≤100A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX
(2)_.Limited only by maximum temperature allowed
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