STP70NF03L Datasheet, PDF (1/9 Pages) STMicroelectronics – N-CHANNEL 30V - 0.008ohm - 70A TO-220/I2PAK LOW GATE CHARGE STripFET™ POWER MOSFET

STP70NF03L
STB70NF03L-1
N-CHANNEL 30V - 0.008Ω - 70A TO-220/I²PAK
LOW GATE CHARGE STripFET™ POWER MOSFET
TYPE
V_DSS
R_DS(on)
I_D
STP70NF03L
STB70NF03L-1
30 V
30 V
< 0.01 Ω
< 0.01 Ω
70 A
70 A
s TYPICAL R_DS(on) = 0.008 Ω
s TYPICAL Q_g = 35 nC @ 10 V
s OPTIMAL R_DS(on) x Q_g TRADE-OFF
s CONDUCTION LOSSES REDUCED
s SWITCHING LOSSES REDUCED
DESCRIPTION
This application specific Power Mosfet is the third
generation of STMicroelectronics unique “Single
Feature Size™” strip-based process. The result-
ing transistor shows the best trade-off between on-
resistance and gate charge. When used as high
and low side in buck regulators, it gives the best
performance in terms of both conduction and
switching losses. This is extremely important for
motherboards where fast switching and high effi-
ciency are of paramount importance.
APPLICATIONS
s SPECIFICALLY DESIGNED AND OPTIMISED
FOR HIGH EFFICIENCY CPU CORE DC/DC
CONVERTERS
3
2
1
TO-220
123
I²PAK
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
V_DS
Drain-source Voltage (V_GS = 0)
V_DGR
Drain-gate Voltage (R_GS = 20 kΩ)
V_GS
Gate- source Voltage
I_D
Drain Current (continuos) at T_C = 25°C
I_D
Drain Current (continuos) at T_C = 100°C
I_DM (q) Drain Current (pulsed)
P_TOT
Total Dissipation at T_C = 25°C
Derating Factor
dv/dt (1) Peak Diode Recovery voltage slope
T_stg
Storage Temperature
T_j
Max. Operating Junction Temperature
(q) Pulse width limited by safe operating area
March 2001
Value
30
30
± 15
70
50
280
100
0.67
4
–65 to 175
175
Unit
V
V
V
A
A
A
W
W/°C
V/ns
°C
°C
(1) ISD ≤70A, di/dt ≤290A/µs, VDD =24 V ; Tj ≤ TJMAX.
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