STP45NF3LL Datasheet, PDF (1/11 Pages) STMicroelectronics – N-CHANNEL 30V - 0.014ohm - 45A TO-220 - TO220FP - D2PAK STripFET II™ POWER MOSFET

STP45NF3LL - STP45NF3LLFP
STB45NF3LL
N-CHANNEL 30V - 0.014Ω - 45A TO-220 - TO220FP - D²PAK
STripFET II™ POWER MOSFET
TYPE
V_DSS
R_DS(on)
I_D
STP45NF3LL
STP45NF3LLFP
STB45NF3LL
30 V
30 V
30 V
<0.018Ω
<0.018Ω
<0.018Ω
45 A
45 A
27 A
s TYPICAL R_DS(on) = 0.014Ω @4.5V
s OPTIMAL RDS(ON) x Qg TRADE-OFF @ 4.5V
s CONDUCTION LOSSES REDUCED
s SWITCHING LOSSES REDUCED
s ADD SUFFIX “T4” FOR ORDERING IN TAPE &
REEL
DESCRIPTION
This application specific Power MOSFET is the
third genaration of STMicroelectronics unique
“Single Feature Size™” strip-based process. The
resulting transistor shows the best trade-off be-
tween on-resistance ang gate charge. When used
as high and low side in buck regulators, it gives the
best performance in terms of both conduction and
switching losses. This is extremely important for
motherboards where fast switching and high effi-
ciency are of paramount importance.
APPLICATIONS
s SPECIFICALLY DESIGNED AND OPTIMISED
FOR HIGH EFFICIENCY DC/DC
CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
V_DS
Drain-source Voltage (V_GS = 0)
V_DGR
Drain-gate Voltage (R_GS = 20 kΩ)
V_GS
Gate- source Voltage
I_D
Drain Current (continuous) at T_C = 25°C
I_D
Drain Current (continuous) at T_C = 100°C
I_DM ( ) Drain Current (pulsed)
P_TOT
Total Dissipation at T_C = 25°C
Derating Factor
E_AS (1) Single Pulse Avalanche Energy
Viso
Insulation Withstand Voltage (DC)
T_stg
Storage Temperature
T_j
Max. Operating Junction Temperature
(q) Pulse width limited by safe operating area
November 2002
3
2
1
TO-220
3
1
D²PAK
3
2
1
TO-220FP
INTERNAL SCHEMATIC DIAGRAM
Value
TO-220/D²PAK
TO-220FP
30
30
± 16
45
27
32
19
180
108
70
25
0.46
0.167
241
--
2500
– 55 to 175
(1) Starting Tj= 25°C, ID= 22.5A, VDD= 24V
Unit
V
V
V
A
A
A
W
W/°C
mJ
V
°C
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