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STP40NF10 Datasheet, PDF (1/11 Pages) STMicroelectronics – N-CHANNEL 100V - 0.024ohm - 50A TO-220/D2PAK/I2PAK LOW GATE CHARGE STripFET™ II POWER MOSFET | |||
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STP40NF10
STB40NF10 - STB40NF10-1
N-CHANNEL 100V - 0.024⦠- 50A TO-220/D2PAK/I2PAK
LOW GATE CHARGE STripFET⢠II POWER MOSFET
TYPE
VDSS
RDS(on)
ID
STP40NF10
STB40NF10
STB40NF10-1
100 V
100 V
100 V
< 0.028 â¦
< 0.028 â¦
< 0.028 â¦
50 A
50 A
50 A
s TYPICAL RDS(on) = 0.024â¦
s EXCEPTIONAL dv/dt CAPABILITY
s 100% AVALANCHE TESTED
s APPLICATION ORIENTED
CHARACTERIZATION
s ADD SUFFIX âT4â FOR ORDERING IN TAPE &
REEL
3
2
1
TO-220
3
1
D2PAK
123
I2PAK
DESCRIPTION
This Power MOSFET series realized with STMicro-
electronics unique STripFET process has specifical-
ly been designed to minimize input capacitance and
gate charge. It is therefore suitable as primary
switch in advanced high-efficiency isolated DC-DC
converters for Telecom and Computer application. It
is also intended for any application with low gate
charge drive requirements.
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
s HIGH-EFFICIENCY DC-DC CONVERTERS
s UPS AND MOTOR CONTROL
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDS
VDGR
VGS
ID(*)
ID
IDM (l)
PTOT
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kâ¦)
Gate- source Voltage
Drain Current (continuous) at TC = 25°C
Drain Current (continuous) at TC = 100°C
Drain Current (pulsed)
Total Dissipation at TC = 25°C
Derating Factor
dv/dt (1) Peak Diode Recovery voltage slope
EAS (2)
Tstg
Single Pulse Avalanche Energy
Storage Temperature
Tj
Operating Junction Temperature
(q) Pulse width limited by safe operating area
(*) Limited by Package
September 2002
Value
100
100
± 20
50
35
200
150
1
20
150
Unit
V
V
V
A
A
A
W
W/°C
V/ns
mJ
â 55 to 175
°C
(1) ISD â¤40A, di/dt â¤600A/µs, VDD ⤠V(BR)DSS, Tj ⤠TJMAX.
(2) Starting Tj = 25°C, ID = 40A, VDD = 50V
1/11
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