STP40N03L-20 Datasheet, PDF (1/7 Pages) STMicroelectronics – N - CHANNEL ENHANCEMENT MODE ”ULTRA HIGH DENSITY” POWER MOS TRANSISTOR

STP40N03L-20
N - CHANNEL ENHANCEMENT MODE
”ULTRA HIGH DENSITY” POWER MOS TRANSISTOR
TYPE
ST P40N03L-20
VDSS
30 V
RDS(on)
< 0.02 Ω
ID
40 A
PRELIMINARY DATA
s TYPICAL RDS(on) = 0.016 Ω
s AVALANCHE RUGGED TECHNOLOGY
s 100% AVALANCHE TESTED
s HIGH CURRENT CAPABILITY
s 175^oC OPERATING TEMPERATURE
s HIGH dV/dt CAPABILITY
s APPLICATION ORIENTED
CHARACTERIZATION
APPLICATIONS
s HIGH CURRENT, HIGH SPEED SWITCHING
s POWER MOTOR CONTROL
s DC-DC & DC-AC CONVERTERS
s SYNCRONOUS RECTIFICATION
3
2
1
TO-220
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
P ar ame t er
VDS
V D GR
V _GS
ID
ID
I_DM(•)
P_{to t}
Drain-source Voltage (VGS = 0)
Drain- gate Voltage (RGS = 20 kΩ)
Gate-source Voltage
Drain Current (continuous) at Tc = 25 ^oC
Drain Current (continuous) at Tc = 100 ^oC
Drain Current (pulsed)
Total Dissipat ion at T_c = 25 ^oC
Derating Factor
dV/dt(1) Peak Diode Recovery voltage slope
Tst g St orage Temperature
T_j
Max. Operating Junction Temperature
(•) Pulse width limited by safe operating area
March 1996
Value
30
30
± 15
40
28
160
90
0 .6
6
-65 to 175
175
Unit
V
V
V
A
A
A
W
W/^oC
V/ns
o_C
o_C
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