STM32L431XX Datasheet, PDF (1/200 Pages) STMicroelectronics – RTC with HW calendar, alarms and calibration

STM32L431xx
Ultra-low-power ARM^® Cortex^®-M4 32-bit MCU+FPU, 100DMIPS,
up to 256KB Flash, 64KB SRAM, analog, audio
Datasheet - production data
Features
• Ultra-low-power with FlexPowerControl
– 1.71 V to 3.6 V power supply
– -40 °C to 85/105/125 °C temperature range
– 200 nA in V_BAT mode: supply for RTC and
32x32-bit backup registers
– 8 nA Shutdown mode (5 wakeup pins)
– 28 nA Standby mode (5 wakeup pins)
– 280 nA Standby mode with RTC
– 1.0 µA Stop 2 mode, 1.28 µA Stop 2 with
RTC
– 84 µA/MHz run mode
– Batch acquisition mode (BAM)
– 4 µs wakeup from Stop mode
– Brown out reset (BOR) in all modes except
shutdown
– Interconnect matrix
• Core: ARM^® 32-bit Cortex^®-M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait-state execution
from Flash memory, frequency up to 80 MHz,
MPU, 100DMIPS/1.25DMIPS/MHz (Dhrystone
2.1), and DSP instructions
• Performance Benchmark
– 1.25 DMIPS/MHz (Drystone 2.1)
– 273.55 Coremark^® (3.42 Coremark/MHz @
80 MHz)
• Energy Benchmark
– 176.7 ULPBench^® score
• Clock Sources
– 4 to 48 MHz crystal oscillator
– 32 kHz crystal oscillator for RTC (LSE)
– Internal 16 MHz factory-trimmed RC (±1%)
– Internal low-power 32 kHz RC (±5%)
– Internal multispeed 100 kHz to 48 MHz
oscillator, auto-trimmed by LSE (better than
±0.25 % accuracy)
– Internal 48 MHz with clock recovery
LQFP100 (14x14)
LQFP64 (10x10) UFQFPN32 (5x5) UFBGA100 (7×7) WLCSP64
LQFP48 (7x7) UFQFPN48 (7x7) UFBGA64 (5x5) WLCSP49
– 2 PLLs for system clock, audio, ADC
• RTC with HW calendar, alarms and calibration
• Up to 21 capacitive sensing channels: support
touchkey, linear and rotary touch sensors
• 11x timers: 1x 16-bit advanced motor-control,
1x 32-bit and 2x 16-bit general purpose, 2x 16-
bit basic, 2x low-power 16-bit timers (available
in Stop mode), 2x watchdogs, SysTick timer
• Up to 83 fast I/Os, most 5 V-tolerant
• Memories
– Up to 256 KB single bank Flash,
proprietary code readout protection
– 64 KB of SRAM including 16 KB with
hardware parity check
– Quad SPI memory interface
• Rich analog peripherals (independent supply)
– 1× 12-bit ADC 5 Msps, up to 16-bit with
hardware oversampling, 200 µA/Msps
– 2x 12-bit DAC, low-power sample and hold
– 1x operational amplifier with built-in PGA
– 2x ultra-low-power comparators
• 15x communication interfaces
– 1x SAI (serial audio interface)
– 3x I2C FM+(1 Mbit/s), SMBus/PMBus
– 4x USARTs (ISO 7816, LIN, IrDA, modem)
– 3x SPIs (4x SPIs with the Quad SPI)
– CAN (2.0B Active) and SDMMC interface
– SWPMI single wire protocol master I/F
– IRTIM (Infrared interface)
• 14-channel DMA controller
• True random number generator
• CRC calculation unit, 96-bit unique ID
May 2016
This is information on a product in full production.
DocID028800 Rev 1
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