STLVDS32B Datasheet, PDF (1/17 Pages) STMicroelectronics – High speed differential line receivers

STLVDS32B
High speed differential line receivers
Features
■ Meets or exceeds the requirements of ansi
TIA/EIA-644 standard
■ Operates with a single 3.3 V supply
■ Designed for signaling rate up to 400 Mbps
■ Differential input thresholds ±100 mV max
■ Typical propagation delay time of 2.5 ns
■ Power dissipation 60 mW typical per receiver
at 200 MHz
■ Low voltage TTL (LVTTL) logic output levels
■ Pin compatible with the AM26LS32,
SN65LVD32
■ Open circuit fail safe
■ ESD protection:
■ 7 kV receiver pins
■ 3 kV all pins vs gnd
Description
The STLVDS32 is a differential line receiver that
implements the electrical characteristics of low
voltage differential signaling (LVDS). This
signaling technique lowers the output voltage
levels of 5 V differential standard levels (such as
TIA/EIA-422B) to reduce the power, increase the
switching speeds and allow operations with a
3.3 V supply rail. This differential receiver
provides a valid logical output state with a 3.3 V
supply rail. It also provides a valid logical output
state with a ±100 mV differential input voltage
within the input common mode voltage range. The
SOP
TSSOP
input common mode voltage allows 1 V of ground
potential difference between two LVDS nodes.
The intended application of this device and
signalling technique is both point-to-point and
multidrop data transmission over controlled
impedance media approximately 100 Ω. The
transmission media may be printed circuit board
traces, backplanes or cables. The ultimate rate
and distance of data transfer depend upon the
attenuation characteristics of the media and noise
coupling to the environment.
The STLVDS32 version is characterized for
operation from -55°C to 125°C.
Table 1. Device summary
Order code
Temperature
range
STLVDS32BDR
-55 to 125 °C
STLVDS32BTR
-55 to 125 °C
Package
SO16 (Tape & reel)
TSSOP16 (Tape & reel)
Packaging
2500 parts per reel
2500 parts per reel
August 2007
Rev. 13
1/17
www.st.com
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