STLC5432 Datasheet, PDF (1/46 Pages) STMicroelectronics – 2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE

STLC5432
2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE
PRELIMINARY DATA
ONE CHIP SOLUTION FROM PCM BUS TO
TRANSFORMER (CEPT STANDARD)
ISDN PRIMARY ACCESS CONTROLLER
(COMPATIBLE WITH ETSI, OPTION 1 AND 2)
HDB3/BIN ENCODER AND DECODER ON
CHIP
MULTIFRAME STRUCTURE HANDLING
BUILT IN CRC4
EASY LINK TO ST5451/MK50H25/MK5027
LINK CONTROLLERS.
DATA RATE: 2048, 4096 AND 8192 Kb/s FOR
MULTIPLEXED APPLICATIONS
FOUR LOOPBACK MODES FOR TESTING
PSEUDO RANDOM SEQUENCE GENER-
ATOR AND ANALYZER FOR ON-LINE, OFF-
LINE AND AUTOTEST
CLOCK RECOVERY CIRCUITRY ON CHIP
64 BYTE ELASTIC MEMORY FOR TIME
COMPENSATION AND AUTOMATIC FRAME
AND SUPERFRAME ALIGNMENT
32 ON CHIP REGISTERS FOR CONFIGURA-
TIONS, TESTING, ALARMS, FAULT AND ER-
ROR RATE CONTROL.
AUTO ADAPTATIVE DETECTION THRESH-
OLD
AUTOMATIC EQUALIZER OPTION
5V POWER SUPPLY
AMI OR HDB3 CODE SELECTION
PARALLEL OR SERIAL MICROPROCESSOR
INTERFACE OPTION
BOTH µp AND STAND ALONE MODE AVAIL-
ABLE
DESCRIPTION
STLC5432, CMOS device, interfaces the multi-
plex system to the physical CEPT Transmission
link at 2048Kb/s. Furthermore, thanks to its flexi-
bility, it is the optimum solution also for the ISDN
application as PRIMARY RATE CONTROLLER.
The receive circuit performances exceed CCITT
recommendation and the line driver outputs meet
the G.703 specifications.
STLC5432 is the real single chip solution that al-
lows the best system flexibility and easy design.
STLC5432 can work either in 2048 or 4096 or
8192 Kbit/s systems programming the CR4 regis-
ter (when parallel micro interface selected).
TQFP44 (10 x 10)
ORDERING NUMBER: STLC5432Q
PIN CONNECTION (Top view)
GNDD
SA/RESET
DIN
A/D0
A/D1
A/D2
A/D3
INT
RCLI
BRDI
DOUT
44 43 42 41 40 39 38 37 36 35 34
1
33
2
32
3
31
4
30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
BXDI
AL0
AL1
A/D7
A/D6
A/D5
A/D4
R/W/WR
LFSX
LFSR
LCLK
D93TL043D
July 1996
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