STI5202 Datasheet, PDF (1/9 Pages) STMicroelectronics – Low-cost set-top box decoder for H.264 and Microsoft VC1

STi5202
Low-cost set-top box decoder for H.264 and Microsoft VC1
Data Brief
Features
■ Single-chip, video decoder including
– Linux^®, Windows^® CE and OS21
compatible ST40 CPU core: 266 MHz
– Transport filtering and descrambling
– Video decoder: VC-1 (including WMV 9),
H.264 (MPEG-4 part 10) and MPEG-2
– SVP compliant
– Windows Media^™ DRM support
– ST40 32-bit superscaler RISC CPU
■ Embedded interfaces
– USB 2.0 host controller/PHY interface
– DVI/HDMI™ output
– Digital audio and video auxiliary inputs
– Low-cost modem
– 100BT ethernet controller with integrated
MAC and MII/RMII interface for external
PHY
Description
The STi5202 is a new generation, set-top
box/DVD decoder chip, and provides very high
performance for low-cost systems. STi5202
includes both VC1 and H.264 video decoders for
new, low bit rate applications.
.
ST40 core 266 MHz
UDI
16 K Icache
MMU
Int. control
32 K Dcache
DDR
SDRAM
5 x 2-ch
PCM out S/PDIF
2-ch ^AudioL
PCM in ^AudioR
SD
video in
32
System
LMI
Audio
DACs
Audio decoder
and interfaces
ST231
core
Digital
video input
USB
2.0
Peripheral I/O
and external interrupts
2x I/F
SmCard
6x GPIO
IR
Tx/Rx
ILC
MAFE
interface
4x
UARTs
PWM
3x
SSCs
2 x PDES
PTI PTI
TSmerger/router
CP
FDMA
Clock
generator
and system
services
Ethernet,
MII/RMII
STBus
Video decoder
VC-1 (inc WMV 9)
H264/MPEG-2
ST231
core
2D gamma
blitter
CUR 3 x GDP
Display
compositor
DVI-HDCP
HDMI
Output stage DENC
DACs
DACs
DEI
Main video
display
Aux video
display
EMI EMPI
TSIN0 TSIN1 TS I/O
NRSS-A
MII/RMII for 100BT
Ethernet
Main video
output (ED)
Main video
output (ED)
YPbPr
Aux video
output (SD)
YC/CVBS
Digital
video
output
Flash
or companion chip
October 2007
Rev 1
For further information contact your local STMicroelectronics sales office.
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www.st.com
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