STH10NA50 Datasheet, PDF (1/11 Pages) STMicroelectronics – N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR

STH10NA50/FI
STW10NA50
N - CHANNEL ENHANCEMENT MODE
FAST POWER MOS TRANSISTOR
TYPE
STH10NA50
STH10NA50FI
STW10NA50
VDSS
500 V
500 V
500 V
R DS( on)
< 0.8 Ω
< 0.8 Ω
< 0.8 Ω
ID
9.6 A
5.6 A
9.6 A
s TYPICAL R_DS(on) = 0.7 Ω
s ± 30V GATE TO SOURCE VOLTAGE RATING
s 100% AVALANCHE TESTED
s REPETITIVE AVALANCHE DATA AT 100^oC
s LOW INTRINSIC CAPACITANCES
s GATE GHARGE MINIMIZED
s REDUCED THRESHOLD VOLTAGE SPREAD
DESCRIPTION
This series of POWER MOSFETS represents the
most advanced high voltage technology. The
optimized cell layout coupled with a new
proprietary edge termination concur to give the
device low RDS(on) and gate charge, unequalled
ruggedness and superior switching performance.
APPLICATIONS
s HIGH CURRENT, HIGH SPEED SWITCHING
s SWITCH MODE POWER SUPPLIES (SMPS)
s DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
ABSOLUTE MAXIMUM RATINGS
Symbol
P ar amete r
V_{D S} Drain-source Voltage (V_GS = 0)
V_{DG R} Drain-gate Voltage (R_{G S} = 20 kΩ)
VGS Gate-source Voltage
I_D
Drain Current (continuous) at T _c = 25 ^oC
I_D
Drain Current (continuous) at T _c = 100 ^oC
IDM(•) Drain Current (pulsed)
Ptot Total Dissipation at Tc = 25 ^oC
Derating Factor
VISO Insulation Withstand Voltage (DC)
Tstg Storage Temperature
T_j
Max. Operating Junction Temperature
(•) Pulse width limited by safe operating area
November 1996
TO-247
3
2
1
TO-218
3
3
2
2
1
1
ISOWATT218
INTERNAL SCHEMATIC DIAGRAM
Val ue
STW/STH10NA50 STH10NA50FI
500
500
± 30
9.6
5.6
6.1
3.5
38
38
150
60
1.2
0. 48

4000
-65 to 150
150
Unit
V
V
V
A
A
A
W
W/^oC
V
o_C
o_C
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