STE800P Datasheet, PDF (1/4 Pages) STMicroelectronics – 10/100 BASE-TX/FX 8 PORT TRANSCEIVER

STE800P
10/100 BASE-TX/FX 8 PORT TRANSCEIVER
PRODUCT PREVIEW
1.0 DESCRIPTION
The STE800P is a high performance Octal Fast
Ethernet physical layer interface for 10BASE-T and
100BASE-TX/ FX applications.
It was designed with advanced CMOS technology to
provide a RMII/SMII for easy attachment to 10/100
Media Access Controllers (MAC) and a physical me-
dia interface for 100BASE-TX / FX of IEEE802.3u
and 10BASE-T of IEEE802.3.
The STE800P supports both half-duplex and full-du-
plex operation, at 10 and 100 Mbps operation. Its op-
erating mode can be set using auto-negotiation,
parallel detection or manual control. It also allows for
the support of auto-negotiation functions for speed
and duplex detection.
2.0 FEATURE
2.1 Industry standard
• IEEE802.3u 100BASE-TX /FX and IEEE802.3
10BASE-T compliant
PQFP208
ORDERING NUMBER: STE800P
• Support for IEEE802.3x flow control
• IEEE802.3u Auto-Negotiation support
• RMII/SMII interface
• Low power, single supply 3.3V CMOS
• Shared MII management interface up to 25
Mbps
Figure 1. BLOCK DIAGRAM FOR 1 PORT
LEDS
TXD(1:0)
TX_ER
TX_EN
MDIC
MDIO
SMII_EN
RXD(1:0)
RX_ER
CRS_DV
REFCLK
HW
Config
Pins
HW Config
Power
Down
100Mb/s
4B/ 5B
Scrambler
NRZ To
Manchester
Encoder
10Mb/s
TX Channel
Parallel ^{NRZ To}
To
NRZI
Serial ^Encoder
Link Pulse
Generator
REGISTERS
Auto
Negotiation
Binary to MLT3
Encoder
10 TX
Filter
Loopback
TRANS-
MITTER
10/100
TXP
TXN
System
Clock
Clock
Generation
100Mb/s
4B/ 5B
Descrambler
Code Align
NRZ To
Manchester
Decoder
10Mb/s
RX Channel
Serial
To
Parallel
NRZI To
NRZ
Decoder
Binary To
MLT3 Decoder
Clock Recovery
Adaptive
Equalization
Baseline
Wander
Link Pulse
Detector
10 RX Filter
Clk Recovery
SMART
Squelch
RECEIVER
10/100
RXP
RXN
November 2001
1/4
This is preliminary information on a new product now in development. Details are subject to change without notice.
REVISION: A06