STE100P Datasheet, PDF (1/29 Pages) STMicroelectronics – 10/100 FAST ETHERNET 3.3V TRANSCEIVER

STE100P
10/100 FAST ETHERNET 3.3V TRANSCEIVER
PRODUCT PREVIEW
1.0 DESCRIPTION
The STE100P, also referred to as STEPHY1, is a
high performance Fast Ethernet physical layer inter-
face for 10BASE-T and 100BASE-TX applications.
It was designed with advanced CMOS technology to
provide a Media Independent Interface (MII) for easy
attachment to 10/100 Media Access Controllers
(MAC) and a physical media interface for 100BASE-
TX of IEEE802.3u and 10BASE-T of IEEE802.3.
The STEPHY1 supports both half-duplex and full-du-
plex operation, at 10 and 100 Mbps operation. Its op-
erating mode can be set using auto-negotiation,
parallel detection or manual control. It also allows for
the support of auto-negotiation functions for speed
and duplex detection.
2.0 FEATURE
2.1 Industry standard
n IEEE802.3u 100BASE-TX and IEEE802.3
10BASE-T compliant
PQFP 64
ORDERING NUMBER: STE100P
n Support for IEEE802.3x flow control
n IEEE802.3u Auto-Negotiation support for
10BASE-T and 100BASE-TX
n MII interface
n Standard CSMA/CD or full duplex operation
supported
Figure 1. BLOCK DIAGRAM
L EDS
LEDS
TX_CLK
TXD[3:0]
TX_ER
TX_EN
MDC
MDIO
100Mb/s
4B/5B
TX Channel
Scrambler
Parallel to
Serial
NRZ To NRZI
Encoder
10Mb/s
NRZ ToManchester
E ncoder
Link Pulse
Generator
REGISTERS
Auto
Negotiation
Binary To MLT3
Encoder
10 TX
Filter
Loopback
TRANSMITTER
TXP
10/100
TXN
Clock
Generation
System
Clo ck
RXD[3:0]
RX_ER
RX_DV
RX_CLK
HW
configuration
pins
HW Config
Power Down
100Mb/s
Descrambler
4B/5B _{Code Align}
RX Channel
Serial to
Parallel
NRZI To NRZ
Decoder
Binary ToMLT3
Decoder
Clock Recovery
Adaptive
Equalization
BaseLine
Wander
10Mb/s
NRZ To Manchester
Encoder
Link Pulse
Detector
10 TX Filter
Clock Recovery
SMART
Squelch
RECEIVER
10/100
RXP
RXN
January 2000
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/29