STA015_10 Datasheet, PDF (1/56 Pages) STMicroelectronics – MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM CAPABILITY

STA015
MPEG 2.5 LAYER III AUDIO DECODER
WITH ADPCM CAPABILITY
„ SINGLE CHIP MPEG2 LAYER 3 DECODER
SUPPORTING:
– All features specified for Layer III in ISO/IEC
11172-3 (MPEG 1 Audio)
– All features specified for Layer III in ISO/IEC
SO28
TQFP44
13818-3.2 (MPEG 2 Audio)
– Lower sampling frequencies syntax exten-
) sion, (not specified by ISO) called MPEG 2.5
t(s ^{„ DECODES LAYER III STEREO CHANNELS,}
DUAL CHANNEL, SINGLE CHANNEL (MONO)
c _{„ SUPPORTING ALL THE MPEG 1 & 2}
u _{SAMPLING FREQUENCIES AND THE}
d _{EXTENSION TO MPEG 2.5:}
ro ^{48, 44.1, 32, 24, 22.05, 16, 12, 11. 025, 8 KHz}
„ ACCEPTS MPEG 2.5 LAYER III
P _{ELEMENTARY COMPRESSED BITSTREAM}
te ^{WITH DATA RATE FROM 8 Kbit/s UP TO 320}
Kbit/s
le _{„ ADPCM CODEC CAPABILITIES:}
o _{– sample frequency from 8 kHz to 32 kHz}
s _{– sample size from 8 bits to 32 bits}
b _{– encoding algorithm: DVI,}
O _{ITU-G726 pack (G723-24, G721,G723-40)}
- _{– Tone control and fast-forward capability}
) _{„ EASY PROGRAMMABLE GPSO INTERFACE}
t(s ^{FOR ENCODED DATA UP TO 5Mbit/s}
(TQFP44 & LFBGA 64)
c _{„ DIGITAL VOLUME CONTROL}
du ^{„ DIGITAL BASS & TREBLE CONTROL}
ro ^{„ BYPASS MODE FOR EXTERNAL AUDIO}
SOURCE
P _{„ SERIAL BITSTREAM INPUT INTERFACE}
te ^{„ EASY PROGRAMMABLE ADC INPUT}
INTERFACE
le_{„ ANCILLARY DATA EXTRACTION VIA I}2_C
o _INTERFACE.
bs ^{„ SERIAL PCM OUTPUT INTERFACE (I2S AND}
LFBGA64
ORDERING NUMBER: STA015$ (SO28)
STA015T$ (TQFP44)
STA015B$ (LFBGA 8x8)
INDICATORS
„ I²C CONTROL BUS
„ LOW POWER 2.4V CMOS TECHNOLOGY
„ WIDE RANGE OF EXTERNAL CRYSTALS
FREQUENCIES SUPPORTED
APPLICATIONS
„ PC SOUND CARDS
„ MULTIMEDIA PLAYERS
„ VOICE RECORDERS
DESCRIPTION
The STA015 is a fully integrated high flexibility
MPEG Layer III Audio Decoder, capable of decod-
ing Layer III compressed elementary streams, as
specified in MPEG 1 and MPEG 2 ISO standards.
The device decodes also elementary streams
compressed by using low sampling rates, as spec-
ified by MPEG 2.5. STA015 receives the input
data through a Serial input Interface. The decoded
signal is a stereo, mono, or dual channel digital
output that can be sent directly to a D/A converter,
by the PCM Output Interface.
OTHER FORMATS)
„ PLL FOR INTERNAL CLOCK AND FOR
OUTPUT PCM CLOCK GENERATION
This interface is software programmable to adapt
the STA015 digital output to the most common
DACs architectures used on the market. The func-
„ CRC CHECK AND SYNCHRONISATION
tional STA015 chip partitioning is described in
ERROR DETECTION WITH SOFTWARE
Fig.1a and Fig.1b.
April 2010
1/56