ST10R172L Datasheet, PDF (1/68 Pages) STMicroelectronics – 16-BIT LOW VOLTAGE ROMLESS MCU

ST10R172L
16-BIT LOW VOLTAGE ROMLESS MCU
s High Performance 16-bit CPU
q CPU Frequency: 0 to 50 MHz
q 40ns instruction cycle time at 50-MHz CPU
clock
q 4-stage pipeline
q Register-based design with multiple
variable register banks
q Enhanced boolean bit manipulation
facilities
q Additional instructions to support HLL and
operating systems
q Single-cycle context switching support
q 1024 bytes on-Chip special function
register area
s Memory Organisation
q 1KByte on-chip RAM
q Up to 16 MBytes linear address space for
code and data (1 MByte with SSP used)
s External Memory Interface
q Programmable external bus characteristics
for different address ranges
q 8-bit or 16-bit external data bus
q Multiplexed or demultiplexed external
address/data buses
q Five programmable chip-select signals
q Hold and hold-acknowledge bus arbitration
support
s One Channel PWM Unit
s Fail Safe Protection
q Programmable watchdog timer
q Oscillator Watchdog
s Interrupt
q 8-channel interrupt-driven single-cycle data
transfer facilities via peripheral event
controller (PEC)
q 16-priority-level interrupt system with 17
sources, sample-rate down to 40 ns
s Timers
DATASHEET
Dedicated
pins
P.6
P.4
P.1 P.0
OSC WDT
XSSP
PLL
DPRAM
ST10 CORE
Interrupt Controller
&PEC
ASC GPT1/2 PWM
P.3
P.5
P.7 Po.2
q Two multi-functional general purpose timer
units with 5 timers
q Clock Generation via on-chip PLL, or via
direct or prescaled clock input
s Serial Channels
q Synchronous/asynchronous
q High-speed-synchronous serial port SSP
s Up to 77 general purpose I/O lines
s No bootstrap loader
s Electrical Characteristics
q 5V Tolerant I/Os
q 5V Fail-Safe Inputs (Port 5)
q Power: 3.3 Volt +/-0.3V
q Idle and power down modes
s Support
q C-compilers, macro-assembler packages,
emulators, evaluation boards, HLL-
debuggers, simulators, logic analyser
disassemblers, programming boards
s Package
q 100-Pin Thin Quad Flat Pack (TQFP)
March 2001
Rev. 1.2
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