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SPEAR-09-H122 Datasheet, PDF (1/37 Pages) STMicroelectronics – SPEAr TM Head600 | |||
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SPEAR-09-H122
SPEAr⢠Head600
Preliminary Data
Features
â ARM926EJ-S core @333MHz.
â 600KByte reconfigurable logic array with 88
dedicated General purposes I/Os, 9 LVDS
channels and 128KByte configurable internal
memory pool.
â Multilayer AMBA 2.0 compliant Bus with fMAX
166MHz
â 32KByte Rom.
â 8KByte common Static Ram.
â Dynamic Power saving features.
â High performance 8 channels DMA.
â Ethernet 10/100/1000 MAC with GMII/MII
Interface to external PHY.
â USB2.0 device with integrated PHY.
â 2 USB2.0 Host with integrated PHY.
â Ext. SDRAM memory interface:
â 8/16bit (DDR1@200MHz)
â 8/16bit (DDR2@333MHz)
â Flashes interface:
â Nand 8/16bit
â Serial (up to 50Mbps).
â 3-SPI Master/Slave up to 40Mbps.
â I2C Master/Slave mode - High, Fast and Slow
speed.
â 2 independent UART up to 460.8 Kbps with
Software Flow Control mode.
â IrDA (Fir-Mir-Sir) from 9.6Kbps to 4Mbps
speed-rate.
â Colour LCD controller:
â up to 1024x768 resolutions.
PBGA420
â 24bpp true colour TFT panel.
â 16bpp DSTN panel.
â 10 GPIOs bidirectional signals with interrupt
capability.
â 88 RAS-GPIOs user customizable bidirectional
signals (up to 4 clocks).
â ADC 10 bit, 1MSPS, 8 analog inputs.
â JPEG codec accelerator.
â 10 independent Timers with programmable
prescaler.
â Real Time Clock.
â WatchDog
â System Controller
â MISC internal control registers.
â JTAG (IEEE1149.1) interface
Description
SPEAr Head600 is a powerful digital engine
belonging to SPEAr family, the innovative
customizable System on chip.
The device integrates an ARM 926 core with a
large set of proven IPs and a big configurable
logic block that allow very fast customization of
unique and/or proprietary solution.
Table 1. Device summary
Part number
Op. temp. range, °C
SPEAR-09-H122
-40 to 85
Package
PBGA420(23x23x1.81mm)
Packing
Tray
February 2007
Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/37
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