SPEAR-09-H022 Datasheet, PDF (1/55 Pages) STMicroelectronics – SPEAr Head ARM 926, 200K customizable eASIC gates, large IP portfolio SoC

SPEAR-09-H022
SPEAr™ Head
ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC
PRELIMINARY DATA
Features
■ ARM926EJ-S - f_MAX 266 MHz,
32 KI - 16 KD cache, 8 KI - KD tcm, ETM9 and
JTAG interfaces
■ 200K customizable equivalent ASIC gates
(16K LUT equivalent) with 8 channels internal
DMA high speed accelerator function and 112
dedicated general purpose I/Os
■ Multilayer AMBA 2.0 compliant Bus with
f_MAX 133 MHz
■ Programmable internal clock generator with
enhanced PLL function, specially optimized for
E.M.I. reduction
■ 16 KB single port SRAM embedded
■ Dynamic RAM interface:
16 bit DDR, 32 / 16 bit SDRAM
■ SPI interface connecting serial ROM and Flash
devices
■ 2 USB 2.0 Host independent ports with
integrated PHYs
■ USB 2.0 Device with integrated PHY
■ Ethernet MAC 10/100 with MII management
interface
■ 3 independent UARTs up to 115 Kbps
(Software Flow Control mode)
■ I²C Master mode - Fast and Slow speed
■ 6 General Purpose I/Os
PBGA420
■ ADC 8 bits, 230 Ksps, 16 analog input
channels
■ Real Time Clock
■ WatchDog
■ 4 General Purpose Timers
■ Operating temperature: - 40 to 85 °C
■ Package: PBGA 384+36 6R (23x23x2.16 mm)
Overview
SPEAr Head is a powerful digital engine
belonging to SPEAr family, the innovative
customizable System on Chips.
The device integrates an ARM core with a large
set of proven IPs (Intellectual Properties) and a
configurable logic block that allows very fast
customization of unique and/or proprietary
solutions, with low effort and low investment.
Optimized for embedded applications.
Order codes
Part number
SPEAR-09-H022
Op. Temp. range, °C
-40 to 85
Package
PBGA420 (23x23x2.16 mm)
Packing
Tray
December 2005
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
Rev 2
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