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SPC570S40E1 Datasheet, PDF (1/68 Pages) STMicroelectronics – Single issue 4-stage pipeline in-order execution core | |||
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SPC570S40E1, SPC570S40E3,
SPC570S50E1, SPC570S50E3
32-bit Power Architecture® microcontroller for automotive ASILD
applications
Datasheet - production data
eTQFP100 (14 x 14 x 1.0 mm) eTQFP64 (10 x 10 x 1.0 mm)
Features
⢠High performance e200z0h dual core
â 32-bit Power Architecture technology CPU
â Core frequency as high as 80 MHz
â Single issue 4-stage pipeline in-order
execution core
â Variable Length Encoding (VLE)
⢠Up to 544 KB (512 KB code + 32 KB data,
suitable for EEPROM emulation) on-chip flash
memory: supports read during program and
erase operations, and multiple blocks allowing
EEPROM emulation
⢠Up to 48 KB on-chip general-purpose SRAM
⢠Multi-channel direct memory access controller
(eDMA paired in lockstep) with 16 channels
⢠Comprehensive new generation ASILD safety
concept
â Safety of bus masters (core+INTC, DMA)
by delayed lockstep approach
â Safety of storage (Flash, SRAM) by mainly
ECC
â Safety of the data path to storage and
periphery by mainly End-to-End EDC (E2E
EDC)
â Clock and power, generation and
distribution, supervised by dedicated
monitors
â Fault Collection and Control Unit (FCCU)
for collection and reaction to failure
notifications
â Memory Error Management Unit (MEMU)
for collection and reporting of error events
in memories
â Boot time MBIST and LBIST for latent
faults
â Check of safety mechanisms availability
and error reaction path functionality by
dedicated mechanisms
â Safety of the periphery by application-level
measures supported by replicated
peripheral bridges and by LBIST
â Further measures on dedicated peripherals
(e.g. ADC supervisor)
â Junction temperature sensor
â 8-region system memory protection unit
(SMPU) with process ID support (tasks
isolation)
â Enhanced SW watchdog
â Cyclic redundancy check (CRC) unit
⢠Dual phase-locked loops with stable clock
domain for peripherals and FM modulation
domain for computational shell
⢠Nexus Class 3 debug and trace interface
⢠Communication interfaces
â 2 LINFlexD modules
â 3 deserial serial peripheral interface (DSPI)
modules
â Up to 2 FlexCAN interfaces with 32
message buffers each
⢠On-chip CAN/UART Bootstrap loader with Boot
Assisted Flash (BAF). Physical Interface (PHY)
can be
â UART
â CAN
⢠2 enhanced 12-bit SAR analog converters
â 1.5 µs conversion time (12 MHz)
â 16 physical channels (fully shared between
the 2 SARADC units)
â Supervisor ADC concept
â Programmable Cross Triggering Unit (CTU)
⢠Single 3.3 V or 5 V voltage supply
⢠4 general purpose eTimer units (6 channels
each)
⢠Junction temperature range -40 °C to 150 °C
September 2015
This is information on a product in full production.
DocID024492 Rev 6
1/68
www.st.com
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