M74HCT7259 Datasheet, PDF (1/11 Pages) STMicroelectronics – 8BIT ADDRESSABLE LATCH/DECODER/RELAIS DRIVER OPEN DRAIN,INVERTING OUTPUT

®
M74HCT7259
8BIT ADDRESSABLE LATCH/DECODER/RELAIS
DRIVER (OPEN DRAIN,INVERTING OUTPUT)
s LOW POWER DISSIPATION
I_CC = 4 µA (MAX.) AT T_A = 25 °C
s COMPATIBLE WITH TTL OUTPUTS
V_IH = 2V (MIN) V_IL = 0.8V (MAX) AT 5V
s OUTPUT DRIVE CAPABILITY
90 LSTTL LOADS
s HIGH CURRENT OPEN DRAIN OUTPUT UP
TO 80 mA
The M74HCT7259 is a high speed CMOS 8 BIT
ADDRESSABLE LATCH/DECODER fabricated in
silicon gate C2MOS technology. It has the same
high speed performance of LSTTL combined with
true CMOS low power consumption.
The M74HCT7259 has single data input (D) 8
LATCH inverted OUTPUTS (Q0-Q7), 3 address
inputs (A, B and C), common enable input
(ENABLE) and a common CLEAR input. To
operate this device as an addressable latch, data
is held on the D input, and the address of the
latch into which the data is to be entered is held
on the A, B and C inputs.
When ENABLE is taken low the data flows
through to the address output. The data is stored
on the positive-going edge of the ENABLE pulse.
All unadressed latches will remain unaffected.
With ENABLE in the high state the device is
deselected and all latches remain in their
previous state, unaffected by changes on the
PRELIMINARY DATA
PACKAGE
DIP
SOP
ORDER CODES
T UBE
T&R
DIP
SOP
M74HCT7259B1R
M74HCT7259M1R M74HCT7259M1RTR
data or address inputs. To eliminate the
possibility of entering erroneous data into the
latches, the ENABLE should be held high
(inactive) while the address lines are changing. If
ENABLE is held high and CLEAR is taken low all
eight latches are cleared to the HIGH (OFF)
state. If ENABLE is low all latches except the
addressed latch will be cleared. The address
latch will instead be the complement of the D
input,effectively implementing a 3 to 8 line
decoder. Internal clamp diodes protect the open
drain outputs against over voltages due to
inductive loads.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 2000
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